Abstract: An electrical host system includes a host and an expandable optical disk recording and playing device. The expandable optical disk recording and playing device includes an expanding interface module, an expanding interface, a storage interface module, an output interface module and a CODEC module. The expanding interface module connects to the expanding interface and the host. The storage interface module connects to a storage device. The CODEC module encodes, decodes or transcodes an audio/video source to generate audio/video data, wherein the audio/video source is inputted from the host through the expanding interface and the expanding interface module. The audio/video data are outputted through the output interface module, or through the storage interface module to the storage device.

Abstract: A data transmission method and a transmission/reception device are described, the data transmission taking place via intermediate memories without the transmitter receiving direct feedback from the receiver regarding the success of the data transmission. Furthermore, at least one transmission and/or reception device is described which forms an interface between at least two control units and has intermediate memories.

Abstract: An expansion device is provided for expanding the functionality of a mobile electronic device while in a mobile mode and/or in a desktop mode. The expansion device may be a media slice that provides multimedia functionality to a mobile electronic device. The media slice may be configured to receive an electromechanical interface from the mobile electronic device and to replicate the electromechanical interface for connecting to another expansion device, such as to a docking station or a port replicator. The expansion device and the mobile electronic device may be connected via a latch mechanism that easily couples and de-couples the devices. An expansion system is also provided that includes a support stand for providing orientation and support features for a computing device and/or an expansion device.

Abstract: This invention enables a USB 1.1 device and a USB 1.1 host to communicate seamlessly with a USB OTG device. The invention complies with both USB 1.1 and OTG specifications. The invention includes the USB 1.1 host, USB 1.1 device and mixed signal circuits to implement USB OTG functions. The mixed signal components are controlled by the USB 1.1 device microcontroller. The invention is a cost effective implementation compared to a custom ASIC design for USB OTG implementation.

Abstract: Methods and apparatus for closed-case removable expansion cards having a removable memory enhance the utility of portable computer hosts, such as PDAs. In both a first and second embodiments the closed-case removable expansion cards preferably use a Type II CompactFlash form factor. In the first embodiment the removable memory is in combination with an external-I/O connector or attached external-I/O device, providing both I/O and memory functions in a single closed-case removable expansion card. This increases the expansion functional density for portable computer hosts, such as PDAs. That is, it increases the amount of functionality that can be accommodated within a given volume allocation for expansion devices. In the second embodiment the removable memory is a private memory for application specific circuitry within the closed-case-removable expansion card. This enhances the utility of portable computer hosts, such as PDAs, as universal chassises for application specific uses.

Abstract: The present invention is directed to a method and apparatus for scheduling a resource to meet quality of service guarantees. In one embodiment of three levels of priority, if a channel of a first priority level is within its bandwidth allocation, then a request is issued from that channel. If there are no requests in channels at the first priority level that are within the allocation, requests from channels at the second priority level that are within their bandwidth allocation are chosen. If there are no requests of this type, requests from channels at the third priority level or requests from channels at the first and second levels that are outside of their bandwidth allocation are issued. The system may be implemented using rate-based scheduling.

Abstract: An apparatus and method for dynamic suppression of spurious interrupts in a computer system. More specifically, there is provided a method that comprises providing a look-up table comprising source IDs and corresponding time delays for each of a plurality of interrupt lines, monitoring each of the plurality of interrupt lines, and updating the time delays in the look-up table based on the monitoring of the interrupt lines, and a system for implementing the method.

Abstract: Two or more very small encapsulated electronic circuit cards to which data are read and written are removably inserted into two or more sockets of a host system that is wired to the sockets. According to one aspect of the disclosure, command and response signals are normally communicated between the host and the cards by a single circuit commonly connected between the host and all of the sockets but during initialization of the system a unique relative card address is confirmed to have been written into each card inserted into the sockets by connecting the command and status circuit to each socket one at a time in sequence. This is a fast and relatively simple way of setting card addresses upon initialization of such a system.

Abstract: An integrated circuit device is described. The integrated circuit device includes a transmitter circuit having an output driver to output data, and a register to store a value representative of an equalization co-efficient setting of the output driver. The value may be determined based on information stored in a supplemental memory device.

Abstract: A hard disk controller having a latency-independent interface comprises a data gate circuit that transmits a data gate signal. A data circuit transmits or receives data under control of the data gate signal. A media gate circuit transmits a media gate signal. A mode selection circuit transmits mode selection information under control of the media gate signal, wherein said data gate signal controls the transfer of data between the hard disk controller and a read/write channel in accordance with the media gate signal.

Abstract: A method and an apparatus to configure a multi-port device are disclosed. The method includes defining a first set of pointers, one for each port of the multi-port device, and storing the first set of pointers in one or more capability structures of the multi-port device.

Abstract: A data transfer memory for reducing the number of components in an electronic module. A master controller circuit provides a transfer start command to a master clock signal generator circuit when receiving an activation detection signal from a power activation detection circuit. As a result, the master clock signal generator circuit generates a basic clock signal, outputs the basic clock signal to an SCL line, and has a master transfer sequencer circuit execute a transfer sequence. The master transfer sequencer circuit transmits a start condition, data stored in the nonvolatile memory via a serial control circuit, and a stop condition to an SDA line synchronously with the basic clock signal.

Abstract: The present invention relates to a USB-based host-to-host networking method capable of transferring information between two hosts. Devices for the method comprise: a register, a pair of FIFO control command transmitters and at least one FIFO bulk transmitter. The register is to temporarily store control commands for information transaction and acts as a buffer. The control command transmitters is to connect two serial interface engines interfacing respectively with the USB interface of each host, by which the information transfer control commands can be delivered from either host. The bulk information transmitter connects to the two serial interface engines for bulk transfer so that any host is capable of issuing the information transfer control commands for executing data transaction between hosts. The present invention provides a new design for networking controller connection by reducing the number of control command transmitters needed, and also capable of transferring bulk information between hosts.

Abstract: A method an apparatus for providing capability information to a shared controller. In one embodiment, a peripheral bus host controller may be shared by a plurality of peripheral devices coupled to a peripheral bus. The peripheral devices may include coder/decoder (codec) circuitry, and may be implemented using a riser card. The host controller may be configured to query the bus for peripheral devices by reading each address on the bus. During the querying process, the host controller may detect one or more peripheral devices coupled to the bus. Following the completion of the querying of the bus, the host controller may then begin reading configuration information from each of the detected devices. The host controller may employ one or more of several different techniques in order to read configuration information from the peripheral device. The configuration information at a minimum includes a device identifier, which may identify the vendor and the function of the device.

Abstract: An evaluation chip is disclosed whose interrupt priority order can be changed freely. A plurality of interrupt priority order determining circuits 20-1 to 2-4 perform a logical operation on a plurality of signals S11 to S14 used for interrupt priority order modifying control that are applied from outside and a plurality of interrupt signals S31-1 to S31-4, and output interrupt modifying signals S24-1 to S24-4. A plurality of interrupt modules 30-1 to 30-4 perform a logical AND operation on the plurality of signals S24-1 to S24-4 and a plurality of interrupt request signals S15-1 to S15-4 that are applied from outside, and output the signals S31-1 to S31-4. An address generating circuit 40 encodes the plurality of signals S31-1 to S31-4 and generates interrupt vector addresses 40. A microcomputer core 50 executes interrupt instructions that have been fetched from an external program memory 100, based on the addresses S40.

Abstract: A multi-service platform system (100) includes a monolithic backplane (104), a slot (108) coupled to the monolithic backplane, wherein the slot is coupled to receive a payload module (102), and a backplane data device (106) integrally embedded in the monolithic backplane, wherein the backplane data device comprises backplane system data (424) for communication to the payload module when the payload module is coupled to the monolithic backplane.

Abstract: A host integrated circuit device can include a host interface circuit that is configured to access a resource associated with the host integrated circuit device in a first device interface format based on a request from a remote integrated circuit device located outside the host integrated circuit device in a second device interface format.

Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

Abstract: A system for extending in length a connection from a universal serial bus (USB) peripheral device to a computer beyond the length enabled by the device hardware.

Abstract: In order to overcome the relatively short battery life and the relatively long delay between the activation and the actual functioning of a typical mobile computing system, the mobile computing system is provided with a personal computer (PC) architecture system and a personal digital assistant (PDA) architecture system, and a common display and shared peripherals. Interfacing to the systems is a super input output or embedded controller (SIO/EC) that acts as a slave device to whatever system has control of computing system. The SIO/EC controls a quick switch which blocks or allows communication along communication busses connecting the systems to the SIO/EC. A user can selectively change, by way of a user interface to the SIO/EC, to whatever system that is desired by the user.