Abstract: When a PC main body wakes up, docking condition discrimination for checking if a LAN controller can be used is made. If the docking condition is satisfied, the LAN controller is set in an operative state, and the PC main body is used while being locked by a lock mechanism. When the WOL function is enabled, a signal WOLEN is activated. In this state, even when the PC main body goes to a sleep state and a signal DOCPWON is turned off, the LAN controller is kept powered. In this case, since the lock mechanism is unlocked, the user can immediately detach the PC main body from a LAN docker and can carry it to a location of his or her choice.

Abstract: Briefly, in accordance with one embodiment of the invention, a system includes: a processor, a voltage regulator, and a memory. The voltage regulator is coupled to the processor to adjust the operating voltage of the processor. The memory is coupled to the processor by a memory bus. The memory has stored on it processor instructions that, when executed by the processor, result in modification of the operating frequency of the processor and result in adjustment of the operating voltage of the processor, based, at least in part, on dynamic changes in the processing load of the processor.

Abstract: Methods and apparatus are described for providing a time-based warning indicating that the energy capacity of a primary energy source of a battery-powered computer has discharged to a low level, and using residual energy of the primary energy source to perform at least one pre-cutoff function. The time-based warning ensures that the warning is provided in a timely manner by overcoming problems caused by analog to digital converter voltage measurement accuracy limitations and flat battery operating voltage versus discharge curves. The primary energy source can be a rechargeable battery, which can also be the sole energy source for the computer. The battery provides power to operate the computer until the battery voltage discharges to the cutoff voltage. The methods and apparatus provide advantages because they reserve the residual energy in the battery to perform at least one pre-cutoff function within a first duration before the battery discharges to the cutoff voltage.

Abstract: A method and apparatus is provided in which Pipelined Packet Transfers (PPT) are implemented. The PPT methodology includes a request phase and a response phase. The PPT request phase involves a PPT request master delivering to a PPT request target a source address, a destination address and an information packet for the interrupt being requested. The PPT response phase involves the PPT request target becoming a PPT response master with the PPT response master delivering to a PPT request master a destination address and a data packet which includes the interrupt processing information. Pipelined Packet transfers (PPT) are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlock.

Abstract: A memory controller with an integrated system management memory region is disclosed. The memory controller receives an SMI acknowledge signal from a processor. The processor then delivers a system management memory address to the memory controller. Instead of fetching SMI handler instructions from the address indicated by the processor, the memory controller instead fetches SMI handler instructions from its integrated system management memory region. At the end of the integrated system management memory's SMI handler, the processor is instructed to fetch instructions from the address originally specified by the processor. In this manner, a BIOS SMI routine may be executed after the integrated SMI routine is executed.

Abstract: A circuit to detect when an accelerated graphics port master device terminates a sideband bus data transfer operation The circuit includes a first register to cyclically generate a predetermined sequence of output signals at a rate determined by a first clock signal, a second register to cyclically generate the predetermined sequence of output signals at a rate determined by a second clock signal (each output signal of the second register having a corresponding first register output signal), and a detector to detect a mismatch between an output signal from the second register and a corresponding output signal from the first register.

Abstract: A circuit card capable of live insertion into an activated electronic system includes a terminal edge from which an edge connector extends a first length. An input decoupling capacitance resides across the edge connector. A backplane within the activated electronic system receives the circuit card, wherein the backplane includes at least one voltage plane, a backplane receptor, and card guide receptor means. The backplane receptor electrically couples the edge connector to the voltage plane when the edge connector engages the backplane receptor. Card guide means are provided for guiding and connecting the circuit card into the backplane, and include at least one conductive member for engaging the card guide receptor means. The conductive member extends a second length from the terminal edge, wherein the second length is greater than the first length. At least one conductive path electrically couples the conductive member across the input capacitance.

Abstract: A method and apparatus for dynamically assigning and enabling a unique functional address for a Universal Serial Bus device. A host assigns the unique functional address during a control transaction. The Universal Serial Bus device disables the default address and enables the unique functional address during a status stage of the control transaction to avoid an error window.

Abstract: A parallel host adapter that interfaces two I/O buses includes at least two independent data channels, a receive data channel and a send data channel. The receive data channel supports at least two data contexts. The parallel host adapter also includes an administrative information channel that couples one of the I/O buses to a memory where administrative information for the parallel host adapter is stored. The send data channel includes a send buffer memory, and a data transfer engine. The data transfer engine is coupled to a first port of the send buffer memory and to a first I/O bus coupled to the parallel host adapter. The send buffer memory is a single data context buffer memory. The receive data channel includes a receive buffer memory, and another data transfer engine. The another data transfer engine is coupled to the first I/O bus and to a first port of the receive buffer memory.

Abstract: In a microcomputer including a CPU, at least one peripheral unit and a bus control unit connected therebetween, the bus control unit is constructed by a bus control circuit for controlling transfer of data, a strobe signal generating circuit for generating a strobe signal and transmitting the strobe signal to the peripheral unit, a flip-flop for sampling a retry requesting signal from the peripheral unit in synchronization with the strobe signal to generate a strobe requesting signal, and a strobe requesting signal detecting circuit for detecting the strobe requesting signal to reset the flip-flop. The bus control circuit receives the strobe requesting signal to transfer data from the CPU to the peripheral unit. The strobe signal generating circuit receives the strobe requesting signal to generate another strobe signal.

Abstract: A method and device are provided for managing a group of electrical devices, e.g., coder/decoders (codecs) in a computer system. Members of a group of electrical devices may be located on the motherboard of the computer system, or off the motherboard, such as on a riser card. An address ID module assigns a primary address to designate one of the devices as a primary device. The primary device performs certain functions that are only performed by a single device. Other devices are designated as secondary devices. A signal indicates whether a member of the group of electrical devices is located on the motherboard. If no device is located on the motherboard, the address ID module designates a primary device and secondary devices from among the devices located on the riser card. A routing module routes output signals from the devices to input pins of a controller.

Abstract: Rapid thread processing is achieved by transferring complete thread contexts between a memory and a context register set. Each thread context is read from a respective memory location in response to either a designated interrupt or an instruction.

Abstract: A real-time power conservation apparatus and method for portable computers employs a monitor to determine whether a CPU may rest based upon a real-time sampling of the CPU activity level and to activate a hardware selector to carry out the monitor's determination. If the monitor determines the CPU may rest, the hardware selector reduces CPU clock time; if the CPU is to be active, the hardware selector returns the CPU to its previous high speed clock level. Switching back into full operation from its rest state occurs without a user having to request it and without any delay in the operation of the computer while waiting for the computer to return to a “ready” state. Furthermore, the monitor adjusts the performance level of the computer to manage power conservation in response to the real-time sampling of CPU activity.

Abstract: What is described here is a system for centrally monitoring and/or controlling at least one unit for endoscopy and particularly for minimally invasive surgery, such as an insufflation means, a pump, a light source and/or a video camera, wherein the unit or units to be controlled are interconnected via interfaces. The inventive system is characterised by the combination of the following features: the units are connected via the interfaces on a self-configuring bus to a BUS master, the BUS master configures the bus automatically, the BUS master monitors the communication on the bus for correct execution.

Abstract: In an information storage apparatus including an uninterruptible power supply (UPS), a sequence of operation from when a power failure occurs to when power of the UPS is turned off is automatically accomplished completely without human power to thereby guarantee user data. For this purpose, the apparatus includes a disk array, a host, and a plurality of UPSs to supply power to the disk array and the host. The UPSs monitor a state change of power on a host side by a host ac control line or an SCSI unit to sequentially execute processing in an order of processing of host termination, processing for cache flush of the disk array, processing of host UPS termination, processing of disk array termination, and processing for termination of disk array UPS. Between the UPSs and the Host and between the UPSs and the disk array, there is provided an interlocking control signal to monitor current states thereof so as to control the respective operations.

Abstract: A bus management system for dynamically allocating bandwidth comprises a bus and a plurality of slave cards coupled to the bus. The slave cards communicate data to the bus and receive data from the bus. The system also includes a master card coupled to the bus. The master card communicates data to the bus and receives data from the bus. The master card comprises a memory, a communication module, and a control module. The memory stores bandwidth information indicating bandwidths allocated to the slave cards. The communication module, coupled to the bus and the memory, communicates with the slave cards according to the bandwidths indicated by the bandwidth information The control module, coupled to the memory, allocates a new bandwidth to a selected slave card and modifies the bandwidth information to indicate the new bandwidth allocated to the selected slave card.

Abstract: A SCSI host bus adaptor provides automatic termination for any port thereof to which no device is attached. The host bus adaptor detects whether single ended (SE) or low voltage differential (LVD) devices are attached thereto and provides the appropriate termination therefor. The last device attached to either port of the host bus adaptor is automatically terminated via an automatic cable termination circuit disposed at the distal end of the cable. The automatic cable termination circuit senses whether single ended (SE) or low voltage differential (LVD) devices are attached to the cable and provides appropriate termination therefor.

Abstract: A system and an integrated circuit device therefor. The integrated circuit device comprises output driver circuitry to output data onto a first external signal line. The output driver circuitry outputs a first portion of data in response to a rising edge transition of a first external clock signal. The output driver circuitry outputs a second portion of data in response to a falling edge transition of the first external clock signal. The integrated circuit device may further include input receiver circuitry to sample data from a second external signal line. The input receiver circuitry samples a first portion of data in response to a rising edge transition of a second external clock signal. The input receiver circuitry samples a second portion of data in response to a falling edge transition of the second external clock signal.

Abstract: A method and system for ordering an interconnect topology to form a ring structure, the topology comprising a number of nodes, are described. In one embodiment, a self identifier for each of the nodes is determined. Further, the self identifier is mapped to a ring identifier for each node. In addition, each node computes the ring identifier of one of its port-connected nodes as its topologically adjacent neighbor identifier.

Abstract: In a system including a plurality of rotatable media type memory devices and disk array storage including in a redundant configuration a plurality of controllers each including a disk array control unit in which a plurality of SCSI bus coupling ports are individually coupled with respective ports of a plurality of host PCs/WSs via SCSI cables, the disk array control unit includes a function to logically transmit a bus operation such as a device or bus reset operation in an arbitrary one of the ports of the disk array storage to other ports. This makes it possible that the ports seems to be physically coupled in a daisy chain when viewed from the host PCs/WSs.