Abstract: A decoder circuit for disabling a defective element in a circuit having redundant replacement elements employs a fuse on a signal path through the decoder circuit from a selection device to a low-impedance output device and a weak default circuit, such as a pull-up transistor, for forcing the state of the output circuit to a low-impedance default state when the fuse is blown.

Abstract: A memory device wherein a voltage dropped by a fixed voltage from a highest operating voltage is divided using a plurality of impedance elements, and common data lines are biased by the divided voltages. Owing to the application of the voltage dropped by the fixed voltage from the highest operating potential, even when resistance values of the impedance elements are reduced, a current to flow through the impedance element path does not increase considerably, and a low power consumption is attained. Owing to the reduced resistance values of the impedance elements, time constants which are determined by the resistances and stray capacitances parasitic to the common data lines are decreased. Thus, the potential changes of the common data lines to arise in correspondence with information stored in a memory cell are quickened, and a data sense time is curtailed, whereby an access time can be shortened.

Abstract: A semiconductor memory device comprises a main memory 101 and a spare memory 102. When a part of the memory cells of the main memory 101 are defective, these defective memory cells are replaced by memory cells in the spare memory 102. The space memory 102 is decoded by the decoder circuit 104. The decoder circuit 104 is capable of decoding the spare memory 102 using a signal of an instruction memory 107. The instruction memory 107 is selectively enabled or disabled by an instruction control circuit 108. Consequently, in a state in which the instruction memory 107 is disabled by the control circuit 108, a spare memory selection signal is not provided from the instruction memory 107 to the decoder circuit 104 and the semiconductor memory device normally decodes the main memory including defective memory cells. As a result, the addresses and the like of the defective memory cells can be determined.

Abstract: A bipolar-CMOS static random access memory device which includes a plurality of static random access memory cells arranged in columns and rows, complementary pairs of bit lines coupled to the cells in each row, word lines coupled to the cells in each row of the cells and a plurality of sense amplifiers and write circuits, with a separate sense amplifier and write circuit coupled to each pair of the complementary bit lines.

Abstract: A CMOS dual port RAM cell is disclosed wherein one of the word lines is parallel to one of the bit lines in the cell. One bit line is accessed through a p-channel transistor while the other bit lines are accessed through n-channel transistors. This configuration permits the cell to use a single well, thus permitting higher density.

Abstract: A memory device having a comparison function includes a plurality of unit cells. Each unit cell is composed of a memory cell, and first and second switching circuits, and a sense line. The first switching circuit is used for comparing input data D and stored data M, and is disposed between the sense line and ground. The second switching circuit is used for comparing input data D and stored data M, and is disposed serially in the sense line. When the stored data is larger than the input data, the output of the sense line becomes a "1" but when the stored data is smaller than the input data, the output of the sense line becomes "0". The memory device can then conduct a magnitude comparison between the stored data and the input data.

Abstract: A dynamic random access memory device having an input/output load connected between a pair of input/output lines and a control circuit used to generate an internal /RAS signal having a reset transition delayed with respect to the same transition of the external /RAS signal. The internal /RAS signal controls at least a word signal applied to a transistor of a selected memory cell and an enable signal applied to an enable transistor, whereby the time the transistor of the memory cell and the enable transistor become non-conductive is delayed with respect to the time at which a transfer transistor connected between each pair of bit lines and the input/output lines becomes non-conductive.

Abstract: Multiple bit parallel data serializers are described for accessing data serially through a port at high video data rates. The serializer preferably comprises a buffer array for storing data at a plurality of SRAM memory locations, sense amplifiers for sensing the stored data, an address decoder for selecting a predetermined memory location of the buffer array for data access by the sense amplifiers, a data latch for the latched buffering of data prior to output to the serial port and a control gate for enabling the gated transfer of data between the sense amplifiers and the output latch.

Abstract: In a read only semiconductor memory, signal lines such as data lines are subjected to an undesired parasitic capacitance which restricts the signal changing rate along the lines. The parasitic capacitance which is driven by a memory cell will become increasingly higher as the memory capacity is increased. According to the present invention, a differential sense amplifier is used to amplify the data signals which are read out of the memory cell. At the same time, a dummy cell is used to generate a reference potential which is to be referred to by the differential sense amplifier. In particular, a dummy cell arrangement is provided wherein each dummy cell includes at least two series-connected semiconductor elements to provide a predetermined dummy cell conductance to establish a reference value.

Abstract: A device, and a corresponding method for its operation, for converting binary electrical signals into optical form and for scrolling the optical signals across an array of liquid crystal cells. The device in its two-dimensional form includes an array of rows of liquid crystal cells of the ferroelectric smectic type, input circuits for applying binary signals to an input cell in each row, and a three-phase clocking circuit connected to the remaining cells in each row, to propagate the states of the input cells rapidly into successive cells across the array, in the same manner as a shift register, but with the signals being stored in optical form for ease of processing in optical processing apparatus.

Abstract: A programmable logic array includes a plurality of semiconductor memory elements, such as FAMOSs, arranged in the form of an array and a sense circuit for receiving data out from the memory elements during read out mode. The present programmable logic array is so structured that the sense circuit is rendered operative for a predetermined time period every time when an input signal to the array changes its state thereby allowing to minimize the power consumption.

Abstract: A three-dimensional tunnel memory device includes a multilayer Langmuir-Blodgett film wherein each layer can store or carry an electric charge. Charges are introduced into one side of the film in a time sequence corresponding to the information to be carried. An electric field is applied between the faces of the film to cause the charge stored by any layer to be transferred to the adjacent layer, and for thus reading out the sequence of charges stored by the film. The multilayer Langmuir-Blodgett film includes memory unit cells each comprising Langmuir-Blodgett films formed, respectively, of different kinds of organic compounds and contacting each other. Electric fields of different magnitudes are applied, respectively, to the film constituting each memory unit cell thereby allowing the stored charge in each film constituting the memory unit cell to hop the tunnel barrier.

Abstract: A method and apparatus for rapid access digital storage and playback of audio information that consists of a large array of solid state random access memory devices connected in a basic multi-group, multi-card, multi-unit configuration that is addressable in one second increments for a selected duration. Storage or playback with requisite signal conversion may be effected by inputting real time decimal address indications to select a designated time and duration of the total memory capacity.

Abstract: Apparatus (82) for providing write protection for EEPROMs (10) intended as a replacement for installed ROM devices, includes write protection circuitry (54) mounted on one surface (88) of a circuit board (84), the other surface (86) receiving the EEPROM, providing a direct plug-in module for retrofit of installed ROM devices.

Abstract: A programmable read-only memory is disclosed in which each of the memory cells is composed of a field effect transistor having a floating gate. The memory is equipped with a word line pull-up circuit which includes a pulse generator generating a pulse signal in response to a change in address signals and a capacitor coupled between the output terminal of the pulse generator and a selected word line, thereby the selected word line taking a level larger than a power supply voltage.

Abstract: A memory device includes a plurality of memory arrays, each having a plurality of memory elements, placed in a memory address space, a memory array selecting device responsive to the address information for designating a given address in the memory address space to select one memory array from the plurality of memory arrays, an address generating device for generating the row and column addresses of the selected memory array, and a setting device for setting memory element information corresponding to the capacity of memory elements in each of the memory arrays, the memory array selecting device responsive to the address information and the memory element information for decoding corresponding to the memory capacity to select the desired memory array, and the address generating device responsive to the address information to generate the row and column addresses of the memory array consisting of memory elements of the maximum capacity.

Abstract: An improved data processing IC chip which can be fabricated with a reduced area is disclosed. The data processing chip includes a plurality of memory blocks provided at different locations. The memory blocks are adapted to be selected by decoded outputs. Each of the memory blocks is provided with a unit decoding circuit for producing a decoded output therefor and the unit decoding circuit is located close to the associated memory block.

Abstract: A digital memory characterized by a plurality of memory cells arranged into a matrix having rows and columns; a row activation circuit for concurrently activating all of the rows of the matrix; and column activation means for concurrently applying either a reset signal or a preset signal to the columns of the matrix. The column activation circuit can include a plurality of digital switches coupled to reset and preset lines associated with each column of the matrix; and reset/preset logic which control the digital switches to selectively couple the reset and preset lines to a constant current source. A complementary, multi-emitter flip-flop memory cell is formed on a semiconductor substrate and includes "riser" portions.

Abstract: A semiconductor device having a vertical transistor consisting of a semiconductor substrate, a first semiconductor region, and a second semiconductor region operatively functioning as a collector, a base, and an emitter of a transistor. By providing a high concentration region in the first semiconductor region, the base width of the transistor is narrowed. In a PROM, a reverse current preventing transistor with such a narrowed base width in each memory cell can be driven by a decoder/driver with a lowered driving power consumption.

Abstract: A delay line digital memory is organized into n signal branches (z.sub.1 . . . z.sub.n), each with m cells which form a serial data or signal flow path. Each cell is comprised of a transfer transistor t with a subsequently following level restorer, regenerator, or buffer circuit p which, however, is omitted in the last cell. Furthermore, n clock signals (s.sub.l . . . s.sub.n) are provided whose frequency (or repetition rate) equals one n-th of the data rate of the digital input signals, and whose effective pulses follow each other in temporal serial succession within one period of the data rate. Clocking (or activation) by clock signals (s.sub.1 . . . s.sub.n) is chosen so that in the first signal branch (z.sub.1) the first transistor is fed with the last clock signal (s.sub.n); in the second signal branch, the first transistor is fed with the next to last clock signal (s.sub.n-1); in the next to last signal branch (z.sub.n-1), the first transistor is fed with the second clock signal (s.sub.