Abstract: An apparatus for and method of coupling a number of data processing components onto a bus for communication amongst the components with a symmetric parallel multi-processing bus system architecture. The bus architecture is particularly applicable to micro computer systems for the interconnection of processing units, memories, and peripherals. The function of arbitration is distributed within the users of the bus permitting ease of coupling relatively slow and fast devices to the same bus. Bus access priority may be easily modified either semi-permanently or by way of rotation. An interrupt line is provided for the communication bus.