Patents Examined by Granvill D Lee
  • Patent number: 7109100
    Abstract: To provide a semiconductor device able to be made uniform in diffusion depth of the impurity in a diffusion layer by a single diffusion and to give the desired threshold voltage and improved in yield and a method of producing the same. The device has a channel layer 16 formed on a substrate 12, a diffusion stop layer 17 formed on the top surface of the channel layer 16, a diffusion layer 18 formed on the top surface of the diffusion stop layer, and a doping region 25 formed adjoining the diffusion stop layer 17 at least at part of the diffusion layer 18 and having an impurity diffused in it, the diffusion stop layer 17 having a slower diffusion rate of the impurity than the diffusion rate of the diffusion layer 18 and stopping diffusion of the impurity from the diffusion layer 18.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: September 19, 2006
    Assignee: Sony Corporation
    Inventor: Mitsuhiro Nakamura
  • Patent number: 7071031
    Abstract: A vertically integrated structure includes a micro-electromechanical system (MEMS) and a chip for delivering signals to the MEMS. The structure includes a metal stud connecting a surface of the chip and the MEMS; the MEMS has an anchor portion having a conducting pad on an underside thereof contacting the metal stud. The MEMS is spaced from the chip by a distance corresponding to a height of the metal stud, and the MEMS includes a doped region in contact with the conducting pad. In particular, the MEMS may include a cantilever structure, with the end portion including a tip extending in the vertical direction. A support structure (e.g. of polyimide) may surround the metal stud and contact both the underside of the MEMS and the surface of the chip. A temporary carrier plate is used to facilitate handling of the MEMS and alignment to the chip.
    Type: Grant
    Filed: May 28, 2003
    Date of Patent: July 4, 2006
    Assignee: International Business Machines Corporation
    Inventors: H. Bernhard Pogge, Michel Despont, Ute Drechsler, Peter Vettiger, Roy Yu
  • Patent number: 7015137
    Abstract: This invention provides a semiconductor device that can ensure that stress on the nitride film is not increased or is reduced, and that can prevent an increase in interconnection capacity. The semiconductor device comprises a underlayer, a base oxide film that is formed on this underlayer, a nitride film pattern with a hole pattern that is provided on this base oxide film, holes that penetrate the base oxide film, an upper oxide film provided on the base oxide film to cover the nitride film pattern, wiring grooves provided through the upper oxide film in which part of the nitride film pattern including the hole pattern is exposed, and wiring metal that fills the holes and wiring grooves. The nitride film pattern is formed with such a shape and size that surrounds the outside of the wiring grooves and is separate from neighbouring nitride film patterns.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: March 21, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Toyokazu Sakata, Hidenori Inui
  • Patent number: 7005364
    Abstract: The invention provides a method for manufacturing a semiconductor device with which an impurity introduction region and a positioning mark region can be formed aligned, based on a common insulating film pattern.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: February 28, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Naoto Niisoe
  • Patent number: 7001843
    Abstract: Methods for forming metal lines in semiconductor devices are disclosed. One example method may include forming a lower adhesive layer on a semiconductor substrate; forming a metal layer including aluminum on the lower adhesive layer; forming an anti-reflection layer on the metal layer; forming a photomask on the anti-reflection layer; performing an initial etching, a main etching and an over-etching for the anti-reflection layer, the metal layer and the lower adhesive layer, respectively, in a region which is not protected by the photomask, using C3F8 as a main etching gas; and removing the photomask residual on the anti-reflection layer.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: February 21, 2006
    Assignee: DongbuAnam Semiconductor, Inc.
    Inventor: Tae-Hee Park
  • Patent number: 6995079
    Abstract: An object of the present invention is to provide an ion implantation method for shortening a down time of an ion implantation apparatus after exposure of a chamber and for improving throughput and a method for manufacturing a semiconductor device. Specifically, the object of the invention is to provide an ion implantation method that can improve throughput during an ion implantation step of B and a method for manufacturing a semiconductor device. The ion implantation method comprises the steps of: introducing an impurity imparting p-type conductivity and H2O in an ion source; ionizing the impurity imparting p-type conductivity; and implanting into a semiconductor film.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: February 7, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Hiroto Shinoda
  • Patent number: 6972244
    Abstract: Wafer level techniques for marking the back surfaces of integrated circuit devices are described. The back surface of the wafer is laser marked while being supported by a mount tape. In some embodiments, the mount tape is sufficiently transparent that the laser light passes through the mount tape and marks the back surface of the wafer. In other embodiments, the laser may actually burn the mounting tape (or portions thereof) during the marking process. The marking may be done on any suitable back surface material including polymeric backcoatings, metalized films or directly on semiconductor materials.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: December 6, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Viraj A. Patwardhan, Nikhil Vishwanath Kelkar, You Chye How, Tian Oon Goh, Soi Chong Low
  • Patent number: 6972237
    Abstract: A method for manufacturing a heterojunction bipolar transistor is provided. An intrinsic collector structure is formed on a substrate. An extrinsic base structure partially overlaps the intrinsic collector structure. An intrinsic base structure is formed adjacent the intrinsic collector structure and under the extrinsic base structure. An emitter structure is formed adjacent the intrinsic base structure. An extrinsic collector structure is formed adjacent the intrinsic collector structure. A plurality of contacts is formed through an interlevel dielectric layer to the extrinsic collector structure, the extrinsic base structure, and the emitter structure.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: December 6, 2005
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Purakh Raj Verma, Shao-fu Sanford Chu, Lap Chan, Jia Zhen Zheng, Jian Xun Li
  • Patent number: 6969682
    Abstract: A system for processing wafers includes a robot moveable within an enclosure to load and unload workpieces into and out of workpiece processors. A processor includes an upper rotor having alignment pins, and a lower rotor having one or more openings for receiving the alignment pins to form a processing chamber around the workpiece. The alignment pins center the workpiece relative to a rotor spin axis and to an etch or drain groove in the upper rotor. A first fluid outlet delivers processing fluid to a central region of the workpiece. The processing fluid is distributed across the workpiece surface via centrifugal force generated by spinning the processing chamber. Purge gas is optionally delivered into the processing chamber through an annular opening around the first fluid outlet to help remove processing fluid from the processing chamber.
    Type: Grant
    Filed: October 24, 2003
    Date of Patent: November 29, 2005
    Assignee: Semitool, Inc.
    Inventors: Kyle M. Hanson, Paul Z. Wirth, Steven L. Peace, Jon Kuntz, Scott A. Bruner
  • Patent number: 6946394
    Abstract: Methods and systems for monitoring semiconductor fabrication processes are provided. A system may include a stage configured to support a specimen and coupled to a measurement device. The measurement device may include an illumination system and a detection system. The illumination system and the detection system may be configured such that the system may be configured to determine multiple properties of the specimen. For example, the system may be configured to determine multiple properties of a specimen including, but not limited to, a characteristic of a layer formed on a specimen by a deposition process. In this manner, a measurement device may perform multiple optical and/or non-optical metrology and/or inspection techniques.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: September 20, 2005
    Assignee: KLA-Tencor Technologies
    Inventors: John Fielden, Ady Levy, Kyle A. Brown, Gary Bultman, Mehrdad Nikoonahad, Dan Wack
  • Patent number: 6929987
    Abstract: In a method of forming a semiconductor device with a first channel layer formed over a portion of a second channel layer, a portion of the second channel underlying the first channel is etched so as to form an overhanging ledge in the first channel, and then a metallic contact disposed on top of the ledge portion is diffused into the first channel by ohmic alloying to form an electrode in the first channel.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: August 16, 2005
    Assignee: HRL Laboratories, LLC
    Inventor: Jeong-Sun Moon
  • Patent number: 6924216
    Abstract: A method of forming the active regions of field effect transistors is proposed. According to the proposed method, shallow implanting profiles for both the halo structures and the source and drain regions can be obtained by carrying out a two-step damaging and amorphizing implantation process. During a first step, the substrate is damaged during a first light ion implantation step and subsequently substantially fully amorphized during a second heavy ion implantation step.
    Type: Grant
    Filed: May 19, 2003
    Date of Patent: August 2, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thomas Feudel, Manfred Horstmann, Rolf Stephan
  • Patent number: 6917061
    Abstract: A heterojunction bipolar transistor is provided that has a reduced turn-on voltage threshold. A base spacer layer is provided and alternately an emitter layer is provided that has a lowered energy gap. The lowered energy gap of the base spacer or the emitter spacer allow the heterojunction bipolar transistor to realize a lower turn-on voltage threshold. The thickness of the emitter layer if utilized is kept to a minimum to reduce the associated space charge recombination current in the heterojunction bipolar transistor.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: July 12, 2005
    Assignee: Microlink Devices, Inc.
    Inventors: Noren Pan, Byung-Kwon Han
  • Patent number: 6897139
    Abstract: A titanium layer and a titanium nitride layer are successively laminated on a substrate and a group III nitride compound semiconductor layer is further formed thereon. When the titanium layer is removed in the condition that a sufficient film thickness is given to the titanium nitride layer, a device having the titanium nitride layer as a substrate is obtained.
    Type: Grant
    Filed: July 18, 2001
    Date of Patent: May 24, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Naoki Shibata, Masanobu Senda
  • Patent number: 6884677
    Abstract: A transistor can include an integrated circuit substrate including spaced apart isolation regions therein and an active region therebetween. A recess is formed in the active region and extends between the spaced apart isolation regions and has a bottom and opposing side wall ends that are defined by facing portions of the spaced apart isolation regions. An electrically insulating layer is formed on the bottom of the recess. A conductive material is formed in the recess on the electrically insulating layer to provide a gate electrode.
    Type: Grant
    Filed: June 2, 2003
    Date of Patent: April 26, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ji-young Kim
  • Patent number: 6883156
    Abstract: A method of designing a circuit includes annotating relative positions of instantiated hierarchical macro cells, which include two or more instantiated standard cells. The relative positions of individual instantiated standard cells may also be annotated. Relative positions of instantiated hierarchical macro cells and individual instantiated standard cells may be altered to form a more compact standard cell configuration. Pin positions may also be annotated by relative position. Relative pin positions may be altered to promote dense signal line routing within the standard cell design. The relative positions of the instantiated hierarchical macro cells and individual instantiated standard cells are converted to absolute grid position locations to form a grid assigned circuit. The grid assigned circuit is then routed.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: April 19, 2005
    Assignee: MIPS Technologies, Inc.
    Inventors: Alex Khainson, Donald C. Ramsey, Jr., Lew Chua-Eoan, Era K. Nangia
  • Patent number: 6878614
    Abstract: A method of forming an integrated circuit device can include forming a plurality of fuse wires on an integrated circuit substrate, and forming an insulating layer on the integrated circuit substrate and on the plurality of fuse wires so that the fuse wires are between the integrated circuit substrate and the insulating layer. A plurality of fuse cutting holes can be formed in the insulating layer wherein each of the fuse cutting holes exposes a target spot on a respective one of the fuse wires, and a cross-sectional area of the fuse wires can be reduced at the exposed target spots. Related structures are also discussed.
    Type: Grant
    Filed: January 7, 2003
    Date of Patent: April 12, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-won Sun, Kwang-kyu Bang, In-ho Nam
  • Patent number: 6878602
    Abstract: A unique electrochemical process fills oxygen vacancies in dielectrics while reducing oxidation of nearby electrodes and conductors. Preferably, an electromagnetic field or bias is applied to a dielectric. The bias causes oxygen vacancies in the dielectric to migrate to the surface of the dielectric. As the oxygen vacancies migrate toward the surface, oxygen ions fill the oxygen vacancies. In one embodiment, a unique plasma treatment provides the oxygen ions that react with the oxygen vacancies. In another embodiment, a unique electrolysis treatment provides the oxygen ions that react with the oxygen vacancies.
    Type: Grant
    Filed: May 22, 2003
    Date of Patent: April 12, 2005
    Assignee: Micron Technology Inc.
    Inventors: Cem Basceri, Gurtej S. Sandhu
  • Patent number: 6875640
    Abstract: A stereolithographic method of applying material to form a protective layer on a preformed semiconductor die with a high degree of precision, either in the wafer stage, when attached to a lead frame, or to a singulated, bare die. The method is computerized and may utilize a machine vision feature to provide precise die-specific alignment. A semiconductor die may be provided with a protective structure in the form of at least one layer or segment of dielectric material having a controlled thickness or depth and a very precise boundary. The layer or segment may include precisely sized, shaped and located apertures through which conductive terminals, such as bond pads, on the surface of the die may be accessed. Dielectric material may also be employed as a structure to mechanically reinforce the die-to-lead frame attachment.
    Type: Grant
    Filed: June 8, 2000
    Date of Patent: April 5, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood
  • Patent number: 6875642
    Abstract: A method for manufacturing thin film and a thin film. The method comprises dipping a substrate in a solution that dries up forming a layer on the surface of the substrate and controlling layer thickness by changing the rate of dipping the substrate in the solution. Before the next dipping after the first dipping, the position of the substrate is changed such that the next dipping will be carried out in a direction which is at an angle to the direction of the previous dipping.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: April 5, 2005
    Assignee: Janesko Oy
    Inventor: Ville Voipio