Abstract: A system for processing semiconductor wafers has process units on a deck of a frame. The process units and the deck have precision locating features, such as tapered pins, for precisely positioning the process units on the deck. Process units can be removed and replacement process units installed on the deck, without the need for recalibrating the load/unload robot. This reduces the time needed to replace process units and restart processing operations. Liquid chemical consumption during processing is reduced by drawing unused liquid out of supply lines and pumping it back to storage.

Abstract: One embodiment of the present invention provides a system that facilitates routing nets between cells in a circuit layout. During operation, the system receives a circuit design to be routed, wherein the circuit design includes multiple circuit blocks that have been placed at specific locations within the circuit layout. Next, the system determines estimated lengths for nets that couple these circuit blocks together. The system then calculates the delay for the nets that couple the circuit blocks using a class one rule. If the delay in a given net is greater than a specified delay, the system inserts a virtual repeater into the given net to decrease the delay.

Abstract: A method of assembling arrays of small particles or molecules using an atomic force microscope to define ferroelectric domains includes depositing a ferroelectric thin film upon a substrate forming workpiece, then using an atomic force microscope having a conductive, tip for generating a pattern on this thin film to define desired nano-circuit patterns. Next, exposure of this thin film to a solution containing chemical species which selectively adsorb or accumulate under the influence of electrophoretic forces in selected regions of this thin film.

Abstract: A disclosed embodiment comprises patterning a conductor in a dielectric in a semiconductor die. The dielectric can be, for example, silicon oxide or a low-k dielectric while the conductor can comprise aluminum, copper, or a copper-aluminum alloy. Thereafter, a blanket of high permeability layer is deposited over the dielectric. The high permeability layer can comprise high permeability materials such as nickel, iron, nickel-iron alloy, or a magnetic oxide. The blanket deposition of the high permeability layer can be accomplished by, for example, a sputtering technique. After depositing the high permeability layer, a portion of the atoms or molecules in the high permeability layer is driven into the underlying dielectric to increase the permeability of the dielectric. As an example, an ion implanter using heavy ions such as silicon ions or germanium ions can be used to drive some of the atoms or molecules in the high permeability layer into the underlying dielectric.

Abstract: A method and system for equivalence checking of logical circuits using iterative circuit reduction and satisfiability techniques provide improved performance in computer-based verification and design tools. By intertwining a structural satisfiability solver and binary decision diagram functional circuit reduction method, computer-based tools can make more efficient use of memory and decrease computation time required to equivalence check large logical networks. Using the circuit reduction technique back-to-back with the simulation technique, optimum local and global circuit reduction are simultaneously achieved. By iterating between the structural and functional techniques, and adjusting the size of sub-networks being analyzed within a larger network, sub-networks can be reduced or eliminated, decreasing the amount of memory required to represent the next larger inclusive network.

Abstract: A method for processing a semiconductor wafer or similar article includes the step of spinning the wafer and applying a fluid to a first side of the wafer, while it is spinning. The fluid flows radially outwardly in all directions, over the first side of the wafer, via centrifugal force. As the fluid flows off of the circumferential edge of the wafer, it is contained in an annular reservoir, so that the fluid also flows onto an outer annular area of the second side of the wafer. An opening allows fluid to flow out of the reservoir. The opening defines the location of a parting line beyond which the fluid will not travel on the second side of the wafer. An apparatus for processing a semiconductor wafer or similar article includes a reactor having a processing chamber formed by upper and lower rotors. The wafer is supported between the rotors. The rotors are rotated by a spin motor. A processing fluid is introduced onto the top or bottom surface of the wafer, or onto both surfaces, at a central location.

Abstract: A method for processing a semiconductor wafer or similar article includes the step of spinning the wafer and applying a fluid to a first side of the wafer, while it is spinning. The fluid flows radially outwardly in all directions, over the first side of the wafer, via centrifugal force. As the fluid flows off of the circumferential edge of the wafer, it is contained in an annular reservoir, so that the fluid also flows onto an outer annular area of the second side of the wafer. An opening allows fluid to flow out of the reservoir. The opening defines the location of a parting line beyond which the fluid will not travel on the second side of the wafer. An apparatus for processing a semiconductor wafer or similar article includes a reactor having a processing chamber formed by upper and lower rotors. The wafer is supported between the rotors. The rotors are rotated by a spin motor. A processing fluid is introduced onto the top or bottom surface of the wafer, or onto both surfaces, at a central location.

Abstract: A method of fabricating a FET having a gate electrode with reduced susceptibility to the carrier depletion effect, includes increasing the amount of n-type dopant in the gate electrode of an n-channel FET. In one embodiment of the present invention, an integrated circuit including NFETs and PFETs is produced with increased n-type doping in the n-channel FET gate electrodes without the use of additional photomasking operations. Prior to polysilicon patterning, a phosphorus doped silica glass (PSG) is deposited over the polysilicon. Subsequent to patterning of the polysilicon, NFET areas are masked, and exposed PFET areas subjected to source/drain extension implant operations. During this sequence, the PSG is removed from PFET areas but remains in the NFET areas. An anneal is performed to drive the phosphorus from the PSG into the NFET gate electrodes. NFET source/drain extensions are formed, and conventional MOSFET processing operations may then be performed to complete the integrated circuit.

Abstract: In a semiconductor device including a substrate which has a primary surface, a conduction wire formed on the primary surface, a semiconductor element which has a secondary surface, a projective electrode formed on the secondary surface, an insulative resin for adhesion which is applied between the primary surface and the secondary surface and which shrinks by hardening thereof, the substrate and the semiconductor element are adhered to each other by the hardening of the insulative resin with the projective electrode and the conduction wire corresponding with each other, so that an electrical connection between the projective electrode and the conduction wire is achieved and that a residual stress is generated in the insulative resin. The residual stress has a maximum value thereof around the projective electrode.

Abstract: A method for embedded flash cell fabrication beyond 0.35 &Xgr;m generation. First, a relatively thick field oxide layer is formed on the P-type substrate to separate the flash cell areas and logic cell area. The flash cell areas are divided into tunnel oxide window and capacitor coupling area. Next, a conventional photolithogrpahy and etching method is used to formed a patterned photoresist on the substrate and expose flash cell areas. Then N-type conductive dopants are implanted into the substrate. For 0.35 &mgr;m generation, the concentration of dopant is increased to 5El7˜1El9 atoms/cm3. Next, the patterned photoresist layer are removed and thicker tunnel oxide and thinner gate oxide layer are formed in one processing step. Next, a doped polysilicon layer is deposited by using a conventional chemical vapor deposition over the tunnel oxide layer to serve as the floating gate of the flash cell.

Abstract: The present invention is directed to a method of forming conductive interconnections in an integrated circuit device to optimize or at least maintain the speed at which signals propagate throughout the integrated circuit device. In one embodiment, the method comprises determining any variation in the size of a contact, as compared to its design size, and varying the size of a conductive line to be coupled to the contact based upon the variation in the size of the contact.

Abstract: The present invention is directed to a method of forming conductive interconnections in an integrated circuit device. In one embodiment, the method comprises forming a dielectric stack comprised of multiple layers, and determining a thickness ratio of the layers of the stack. The method further comprises determining an etching process to be performed on the dielectric stack to define an opening for a conductive interconnection based upon the determined thickness ration, and performing the determined etch process on the dielectric stack.

Abstract: In manufacturing a semiconductor device, an amorphous silicon layer with a predetermined thickness to be electrically connected to a silicon substrate is formed on a silicon oxide film formed on the silicon substrate. Nuclei are formed on the surface of the amorphous silicon layer by irradiation of a predetermined material while the amorphous silicon layer is annealed at the first temperature. Convexities are formed on the surface of the amorphous silicon layer using the nuclei as centers while the amorphous silicon layer having the nuclei is annealed at the second temperature lower than the first temperature.

Abstract: Electro-optical device characterized by having been formed into an individual unit with an integral optical element, and method to form the device. An optical element, for instance a length of cylindrical microlens, is aligned with a diode strip having a plurality of diodes, for instance laser diodes, and attached to the lens. Subsequent to this attachment, the composite structure consisting of the diode strip having attached to it the lens is sectioned into individual diodes, each of which has a integral lens attached thereto.