Patents Examined by Greg J. Lamarre
  • Patent number: 6901546
    Abstract: A device for fault testing in a microprocessor chip provides a LBIST circuit which has a first reference signature. A loading unit is further provided for receiving and outputting a set of masking data. A file unit connected to the loading unit is yet further provided for receiving the masking data. A masking unit connected to the file unit is yet further provided for generating a second reference signature based on the masking data from the file unit and a scanning data from a scan string in the chip. And, a signature logic connected to the output of the masking unit is yet further provided for compressing the second reference signature and inputting the compressed second reference signature to the LBIST circuit, wherein the compressed second reference signature replaces the first reference signature.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: May 31, 2005
    Assignee: International Business Machines Corporation
    Inventors: Sam Gat-Shang Chu, Joachim Gerhard Clabes, Michael Normand Goulet, Johnny J. Leblanc, James Douglas Warnock
  • Patent number: 6898748
    Abstract: A test circuit for integrated circuit devices shortens test times, and reduces the length of the test pattern and the number of external terminals. The test circuit is provided between first and second target circuits, and incorporates a first selection section for selecting one of a first output signal from the first target circuit, a second output signal from the second target circuit, and a test signal indicating a test pattern input via a test pattern input terminal. A temporarily data storage section stores the signal selected by the first section, and a second selection selects one of temporarily stored data or the second output signal. The results are provide to the first target circuit. A third selecting section is provided; for selecting one of the temporarily stored data signal or the first output signal, and providing the selected signal to the second target circuit.
    Type: Grant
    Filed: October 17, 2000
    Date of Patent: May 24, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Yoshiyuki Nakamura
  • Patent number: 6888538
    Abstract: A low cost x-y digitising system is provided for use in consumer electronic devices, such as portable digital assistants, mobile telephones, web browsers and the like. The digitiser includes a resonant stylus, an excitation winding for energising the resonant stylus and a set of sensor windings for sensing the signal generated by the stylus, from which the x-y position of the stylus is determined.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: May 3, 2005
    Assignee: Synaptics (UK) Limited
    Inventors: David T. E. Ely, Andrew N. Dames
  • Patent number: 6854077
    Abstract: A communication system 100 employs turbo encoding having a turbo interleaver 106 that interleaves input data 101 efficiently with little use of system resources. The turbo interleaver 106 reads address locations of the data bits into an interleaver matrix array 206 row by row and interleaves the address locations by bit reversal of the row indexes with accompanying permutation of the corresponding address locations in the rows of the matrix 206, bit reversal of the column indexes with accompanying permutation of the corresponding address locations in the columns of the matrix 206 and shifting the address locations within each row a predetermined number of column locations based on the particular row number.
    Type: Grant
    Filed: February 2, 2001
    Date of Patent: February 8, 2005
    Assignee: Motorola, Inc.
    Inventors: Jiangnan Chen, Louay Jalloul