Abstract: A multi-dimensional, multi-nodal routing mechanism is described for relaying information from node to node using a header consisting of route descriptor bits. Each node's receiver/transmitter pair changes states as the information is guided to the destination node. The message is propagated over several nodes simultaneously to traverse the nodes and reach the destination node quickly. When the final node is reached, all alternate communication routes are freed.

Abstract: A memory including several modules with each module receiving at the input requests coming from a processor and furnishing at the output the responses to these requests. The requests are transmitted to the input of each module via an input shift register. The responses coming from a module are transmitted to the input of a processor via an output shift register. The number of stages of the input shift register is different for each of the modules and the total number of stages for the input and output shift registers associated with one of the modules is constant and independent of the module in question.

Abstract: A cache memory which includes a cache controller formed on a single substrate. A plurality of the identical memories may be used in an array. The memories themselves determined how many other memories are in an array and each of their relative positions in the array. From this information, each memory sets the range of its set fields and the size of its tag fields. This is done on reset with the configuration information being distributed among the memories themselves, without being centrally stored, and in a manner transparent to the software.