Patents Examined by Gregory Key
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Patent number: 4868639Abstract: In a semiconductor device which has an air tight metal package containing a high frequency wave range circuit element and which has a waveguide-coaxial line transformation structure, a metal terminal for the waveguide-coaxial line is air-tightly attached directly in a hole of a base of the metal package with a dielectric spacer, usually by glass fusion, whereby the thickness of the base may be reduced and attachment of the terminal to the base is simplified.Type: GrantFiled: August 10, 1987Date of Patent: September 19, 1989Assignee: Fujitsu LimitedInventors: Hiroshi Mugiya, Mitsuo Hasegawa, Youichi Arai
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Patent number: 4853761Abstract: A semiconductor device obtained by using plastic molding to obtain an ultraviolet ray erasable type EPROM semiconductor chip in which an ultraviolet ray transparent resin film is inserted between the semiconductor chip and the molding material so as to cover a portion of the surface or the whole surface of the semiconductor chip except for the surfaces of the wire bonding electrodes.Type: GrantFiled: March 13, 1987Date of Patent: August 1, 1989Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Shingo Ikeda
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Patent number: 4845545Abstract: A flat thin package for semiconductor die has rigid leads extending perpendicularly from its length which can be plugged into a printed circuit board socket. The package has a low profile above the surface of the printed circuit board.Type: GrantFiled: February 13, 1987Date of Patent: July 4, 1989Assignee: International Rectifier CorporationInventors: Howard M. Abramowitz, Jerry R. Carpenter, Dennis Meddles
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Patent number: 4839717Abstract: A ceramic semiconductor package suitable for high frequency operation includes internal and external ground planes formed on opposite faces of a ceramic base member. The internal ground plane is connected to a ground ring formed on the packaged semiconductor device, and both ground planes are interconnected about the periphery of the package. In this way, a uniform and continuous ground is provided to minimize variations in signal transmission line impedance.Type: GrantFiled: June 7, 1988Date of Patent: June 13, 1989Assignee: Fairchild Semiconductor CorporationInventors: William S. Phy, James M. Early, Kevien J. Negus
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Patent number: 4821096Abstract: A device for protecting semiconductor devices during excess energy events. The device uses p-MOS field effect transistors in a common n-well with a common gate configuration. An input is coupled to the source of a first p-type transistor and to the n-well. The first transistor is coupled through a series resistor to a second p-MOS transistor. The drains of each transistor are coupled to ground and gate aided breakdown reduces the voltage at which breakdown occurs.Type: GrantFiled: December 23, 1985Date of Patent: April 11, 1989Assignee: Intel CorporationInventor: Timothy J. Maloney
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Patent number: 4814857Abstract: The present invention provides a pluggable, high density, reliable integrated circuit package. The package has a plurality of integrated circuit chips mounted on a multilayer ceramic substrate. Input-output signals are provided to the module by means of mating male female input-output pins which are located on the bottom of the module. Power is provided to the module from a multilayer ceramic frame through an edge connector that is an integral part of the mulltilayer ceramic substrate. Matching circuit vias located on the edge of the multilayer ceramic substrate and on the edge of the multilayer ceramic frame are cut and tinned with tin-lead to provide power input connections. When the module is plugged into the circuit board the edge connectors on the module mate with the edge connectors in the ceramic frame. Since the frame is made of the same material as the module substrate, the power connectors have excellent thermal match and they are highly reliable.Type: GrantFiled: February 25, 1987Date of Patent: March 21, 1989Assignee: International Business Machines CorporationInventor: George G. Werbizky
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Patent number: 4812897Abstract: A semiconductor element mounted on a substrate is sealed with a silicone gel which has a complex modulus of elasticity such that breakage of solder bumps due to thermal fatique occurs preferentially by shear stress thereto due to a difference between thermal expansion coefficients of the semiconductor element and the substrate, not by tension thereto due to thermal expansion of the silicone gel between the semiconductor element and the substrate.Type: GrantFiled: September 1, 1987Date of Patent: March 14, 1989Assignee: Nippondenso Co., Ltd.Inventors: Ryoichi Narita, Toshio Sonobe, Hitoshi Ito, Junji Ishikawa, Osamu Takenaka, Junji Sugiura
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Patent number: 4809058Abstract: An integrated circuit device comprising a wiring substrate on one surface of which integrated circuit chips are mounted, a power source substrate of a laminated structure provided in contact with the other surface of the wiring substrate and formed by alternately laminating a plurality of feeding conductor layers of a heat conductive metal and a plurality of electrically insulating layers of an electrically insulating material, and bonding together the laminated layers, a means for electrically connecting the wiring substrate and the power source substrate to each other, and a heat radiating means inserted in at least either the feeding conductor layers or the electrically insulating layers and adapted to radiate the heat, which occurs in the power source substrate, to the outside thereof.Type: GrantFiled: December 15, 1986Date of Patent: February 28, 1989Assignee: Hitachi, Ltd.Inventors: Takao Funamoto, Ryoichi Kajiwara, Mituo Katou, Takeshi Matsuzaka, Tomohiko Shida, Hiroshi Wachi, Kazuya Takahashi, Masatoshi Watanabe, Minoru Yamada, Keiichirou Nakanishi, Katuo Sugawara
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Patent number: 4801995Abstract: A semiconductor device includes a metal film, not in ohmic contact with a guard ring region (a second region). The metal film is formed on that surface portion of an insulating film under which the guard ring region is formed to surround a base region (a first region) of a planar transistor. In this arrangement, a planar semiconductor device with a high withstand voltage, which is free of short-circuiting between electrodes upon the measurement of the withstand voltage and involves no degeneration of the withstand voltage resulting from an atmospheric humidity, can be obtained. The metal film, which is not in contact with the guard ring region, is "electrically floated", i.e., is not in contact with any area inclusive of the guard ring region.Type: GrantFiled: December 20, 1985Date of Patent: January 31, 1989Assignee: Kabushiki Kaisha ToshibaInventor: Masaaki Iwanishi
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Patent number: 4800419Abstract: A composite support assembly for an integrated circuit chip includes a rigid lead frame that is attached to a relatively thin flexible tape-like structure. The tape-like structure is etched with inner lead fingers and outer lead fingers to allow a short pitch, high density arrangement of the lead fingers, thereby enabling bond wires that connect an IC chip to the support assembly to be shortened. As a result, a significant increase in the number of leads is realized, using a standard size IC package.Type: GrantFiled: January 28, 1987Date of Patent: January 24, 1989Assignee: LSI Logic CorporationInventors: Jon Long, V. K. Sahakian
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Patent number: 4758873Abstract: A peaking capacitor for use with a differential input stage in an integrated circuit. The stage includes emitter degeneration resistors and a peaking capacitor coupled between the emitters. The capacitor is formed of MOS capacitors located over thinned oxide portions that lie within the confines of doped regions forming PN junctions with the semiconductor substrate. The doped regions are spaced apart by a distance that will result in depletion region reach-through at a voltage that is lower than the thinned oxide breakdown voltage. Thus, the structure is self-protecting and therefore resistant to electrostatic discharge damage. The capacitor that is formed has a value that is determined accurately by the area of the thinned oxide. It also has a low stray capacitance which makes it useful as a peaking capacitor.Type: GrantFiled: May 16, 1986Date of Patent: July 19, 1988Assignee: National Semiconductor CorporationInventor: Dennis M. Monticelli
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Patent number: 4754318Abstract: A semiconductor device has a semiconductor substrate, a first insulating layer formed on the substrate, a conductive body formed on the first insulating layer, a second insulating layer formed on the first insulating layer and the conductive body and having a contact hole formed at a contact area to reach the conductive body, and a first conductive layer formed on the second insulating layer and the conductive body. The conductive body has a conductive member formed on the first insulating layer in the contact area, and a second conductive layer formed on the first insulating layer and the conductive member.Type: GrantFiled: September 29, 1986Date of Patent: June 28, 1988Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Momose, Hideki Shibata, Hiroshi Nozawa