Abstract: The invention proposes the separate processing of the phase and amplitude of multi-amplitude digital modulation techniques, such as a QAM. The phases are differentially modulated and the amplitudes coherently processed. Also proposed is a method to correct the amplitude distortion of the symbols on each subcarrier, either from the QAM signal itself or from any PSK signal, if available. The invention shows that differential modulation/demodulation of multi-amplitude signals with no equidistant phases such as QAM is possible. Complex equalizer means to perform a channel estimation is no more needed as for coherent systems. Further, no pilot sucarriers are needed, thus the bandwidth efficiency is much higher. Furthermore, the frequency snychronization of differential demodulated signals is less complex. An implementation proposal of the new modulation/demodulation technique is described.

Abstract: A baud clock (15) for use by a serial communication interface (67) is generated by dividing a base clock of the serial communication interface by one of a plurality of possible composite divisors (DEG). Each composite divisor is indicative of a minimum time interval by which adjacent pulses of the baud clock are to be separated, and further indicates that at least one pair of adjacent pulses within each symbol interval of the baud clock are to be separated by an extended time interval which is longer than the minimum time interval.

Abstract: A bandwidth efficient advanced modulation waveform modem using concatenated iterative turbo coding and continuous phase modulation is disclosed. A demodulator in the modem has a turbo decoder and a decision feedback carrier and time tracking algorithm to track a carrier and adjust timing. The decision feedback carrier and time tracking algorithm may use an APP decoder as a decision device to provide symbol decisions at a high error rate and low latency for a coded input data stream. A symbol phase estimator produces a symbol phase error estimate from the symbol decisions. An erasure decision function decides which symbol decisions are correct and which symbol decisions are erasures. A carrier tracking function receives the symbol phase error estimates when the symbol decisions are correct and receives erasure inputs when the symbol decisions are erasures to maintain carrier tracking.

Abstract: An impulse response matrix of a received signal in a TDMA communications system is approximated using a plurality of indirect variables of a linear complex vector. The indirect variables are used for synchronizing to the received signal and for tracking and frequency offset estimation during successive samples of the received signal, the samples being equalized in dependence upon the indirect variables. A demodulated signal is derived from the equalized received signal samples. Individual synchronization and tracking units, and a single equalizer, can be provided for a two-antenna receiver. Tracking errors can be used to adapt a parameter of the equalizer to reduce interference in the received signal.

Abstract: A digital signal receiver and a method for receiving a digital signal. The receiver includes an equalizing unit for compensating for an amplitude distortion of a received signal, an original signal decision unit for deciding an original signal from a signal which is compensated for the amplitude distortion, a carrier recovering and phase lock detecting unit for detecting a phase error between an input of the original signal decision unit and the decided original signal, and outputting a phase lock signal, a re-rotating unit for restoring the signal from the original signal decision unit to its original state and outputting a restored signal to the equalizer, and a coefficients updating unit for receiving the phase lock signal from the carrier recovering and phase lock detecting unit and the restored signal from the re-rotator unit, generating an error for updating the coefficients of the equalizer, and updating the coefficients of the equalizer.

Abstract: A synchronizing signal processing circuit for use in a video apparatus such as a display apparatus and an information recording/reproducing is disclosed. The synchronizing signal processing circuit is capable of not only removing false synchronizing pulses included in incoming synchronizing signals and compensating for missing signals, but also causing its output to follow its input quickly after a phase of the incoming synchronizing signals has shifted abruptly.

Abstract: A method, apparatus and system detects a loss of synchronization between a transmitter and a receiver in a multiple-carrier communication system such as an OFDM system. A phase-frequency synchronization detector determines when the receiver has lost synchronization with the transmitter based on a phase-frequency relationship of plurality of pilot signals transmitted at different frequencies from the transmitter and received at the receiver. A loss of synchronization is detected when a slope of a line defined by the phase-frequency relationship exceeds a timing threshold more at a rate in excess of an occurrence threshold within a time period.

Abstract: A subscriber device (2) includes a long code generator (12) and a modifier (30) for generating a spread bit stream with a predetermined error pattern that is transmitted by a transmitter (16) at the subscriber device (2) to a base station (3). The base station (3) identifies the current subscriber device properties by identifying the error pattern and subsequently compares the current subscriber device properties with a knowledge base of subscriber device software properties associated with the error pattern in the spread bit stream. The knowledge base is stored in a memory source (4).

Abstract: A GPS receiver receives GPS spread spectrum communication signals subject to carrier demodulation and code phase autocorrelation using tightly coupled Kalman filter residual estimation based on Ricatti matrix computation for generating code phase errors and carrier phase errors for improved code phase tracking and carrier phase tracking in feedback loops for use in navigation systems.

Abstract: The frame synchronizing circuit establishes frame synchronization by detecting a sync pattern laid in an incoming frame. The frame synchronization circuit comprises a first frame synchronizing unit and a second frame synchronizing unit. The first and second synchronizing units synchronize with a first pattern, a second pattern at a first position and a second position, respectively. Thereafter, when the first position used for the synchronization by the first frame synchronizing unit is found to be in error, the first frame synchronizing unit synchronizes with the second pattern at the second position used by the second frame synchronization unit.

Abstract: A network receiver is configured for receiving a modulated carrier signal representing a data frame from a network transmitter via a network medium, the receiver includes an adaptive equalizer with a finite impulse response filter for filtering the received signal. The filter utilizes a plurality filter coefficients. A cache stores a plurality of sets of coefficients for use by the filter and the equalizer selects a set of coefficients for receiving the data frame.

Abstract: Disclosed is a method for wireless signal transmission of signals from an array of two or more antennas, in which each signal to be transmitted is selected from a constellation of unitary space-time signals. Each unitary space-time signal is a unitary matrix, in which each column represents a respective antenna, each row represents a respective time interval, and each element represents a complex amplitude to be transmitted by a given antenna during a given time interval. In specific embodiments of the invention, the matrices of the signal constellation form a non-Abelian group having a positive diversity product, or a coset of such a group. In other embodiments, the signal constellation is a subset of such a group, and its multiplicative closure forms a finite non-Abelian group having a positive diversity product.

Abstract: The invention is a communication system having a series of output modules that provide continuous synchronization output signals. Each output module has a driver assembly has a driver output and a backup selector output that is capable of driving a failed next driver assembly. A sensor detects the failure of the driver output and generates a select signal in the failure state. A selector receives the driver output, a backup driver output, the select signal, and a select signal from the next driver assembly. The selector normally selects the driver output, but in response to a failure state from the select signal, isolates the failed driver output. The previous driver assembly transmits a backup selector output to the failed driver assembly to maintain a continuous driver output. The transformers are preferably placed on a separate card to reduce the thermal degradation of nearby electronics. As transformers rarely fail, replacing them when a card fails is wasteful.

Abstract: A digital communication system comprises a transmitter for sequentially transmitting predetermined format data; and a plurality of receivers 102 each including a data selecting apparatus 104 for selecting required data from received data group and outputting selected data. The transmitter transmits data to the receivers in one of a first transmission mode having group destination directing information indicating that the data is to be transmitted to a receiving group consisting of predetermined receivers of the plurality of receivers, group specifying information for specifying a receiving group of receiving groups to which the data is to be transmitted, and in-group identification information for identifying a receiver in an arbitrary receiving group to which the data is to be transmitted, a second transmission mode having the group destination directing information and the group specifying information are included in the data, and a third transmission mode having the group destination directing information.

Abstract: A method and apparatus are disclosed for reducing the computational complexity of the RSSE technique. The apparatus and associated method does not assume that the signal energy of a pulse that has gone through a channel is always concentrated primarily in the initial taps, as is true for a minimum phase channel. The present invention, however, recognizes that the signal energy is often concentrated in just a few channel coefficients, with the remaining channel coefficients being close to zero. A receiver apparatus and associated method is disclosed for reducing the number of channel coefficients to be processed with a high complexity cancellation algorithm from L to V+K which contain the majority of the signal energy, while processing the L−(K+V) non-selected coefficients with a lower complexity algorithm. By only processing the intersymbol interference caused by a reduced number of channel coefficients (i.e.

Abstract: In a frequency converter, a phase-locked loop generates a local-oscillation signal having a low frequency, of a plurality of local-oscillation signals having different frequencies, based on an intermediate frequency beacon signal that results from mixing a predetermined beacon signal with the local-oscillation frequency signal. Even if the phase-locked loop is used to generate the low frequency local-oscillation signal only, a frequency offset and a phase noise taking place in remaining high frequency local-oscillation signals are compensated for or canceled out. The frequency converter thus results in a high frequency accuracy. This arrangement reduces the number of bulky, costly and power-consuming phase-locked oscillators, typically used in the quasi millimeter band or the millimeter band. A simplified, compact frequency converter is thus provided, reducing both installation and operating costs.

Abstract: A communication system (20) employs fixed rate channel-optimized, trellis-coded quantization (COTCQ) at a plurality of diverse encoding bit rates. COTCQ is performed through a COTCQ encoder (40) and COTCQ decoder (54). The COTCQ encoder and decoder (40,54) each include a codebook table (62) having at least one codebook (64) for each encoding bit rate. Each codebook (64) is configured in response to the bit error probability of the channel (26) through which the communication system (20) communicates. The bit error probability influences codebooks through the calculation of channel transition probabilities for all combinations of codewords (90) receivable from the channel (26) given all combinations of codewords (90) transmittable through the channel (26). Channel transition probabilities are responsive to base channel transition probabilities and the hamming distances between indices for codewords within subsets of the transmittable and receivable codewords.

Abstract: Methods and apparatus for implementing digital resampling circuits which create one or more bitstreams which include samples at desired rates, from an input bitstream having a fixed sample rate, are described. The resampling circuits of the present invention achieve the desired sample rates by performing digital interpolation on samples included in the input signal. The interpolation is performed using a filter, e.g., an all-pass infinite impulse response filter which produces an output as a function of a controllable signal delay.

Abstract: A direct conversion receiver which compensates for interfering signals introduced during processing. Direct conversion is achieved using direct detection techniques which introduce interfering signals which become inseparable from the wanted signal. A pilot signal (202) is added to an input RF signal (200) prior to passing the summed signal (206) to four separate paths (210, 212, 214, 216). Signal (206) is modulated so that the phase is different in each path using local oscillator signals and switches (230, 232, 234, 236), and then digitised by ADCs (260, 262, 264, 266). Correction is introduced into respective paths (210, 214) by cancellation loops (310, 314) to compensate for unwanted signals prior to the paths being grouped so that the pairs of digitised signals (272, 300; 276; 304) which are 180° out of phase with one another are subtracted to provide output inphase and quadrature signals (220, 224).

Abstract: An apparatus comprising three sampling circuits to sample incoming data and a quarter clock. A clock generation unit is included to generate at least three sampling clocks from a local clock. Each of the three sampling clocks are configured to sample the incoming data and the quarter clock. A phase detector is also included to detect a phase difference between the quarter clock and the local clock and to generate a recovered quarter clock. A delay line is further included to delay the sampled incoming data and the recovered quarter clock by the detected phase difference.