Abstract: A method for locating phase faults in a microgrid in off-grid mode. The method includes obtaining a grid topology of the microgrid having at least two busbars and determining the position of all circuit breaker position of the grid topology. Further, acquiring measurement data which includes current magnitude and voltage magnitude. Monitoring the at least two busbars for a voltage dip in one of phase-to-phase or phase-to-neutral voltages. On detecting a voltage dip, determining a defect phase having a minimum phase-to-neutral voltage value. And for the defect phase performing busbar analysis and feeder analysis, using phase-directional information.

Abstract: A switching converter is provided that includes a power MOSFET, a controller having a drive pin connected to a gate terminal of the power MOSFET, and a resistor connected to the gate terminal. A compensation time selection circuit is included that has compensation times stored therein. A compensation time is selected from the compensation times based on a value of the resistor and stored in the controller. The selected compensation time compensates for an inherent delay in switching the power MOSFET to an ON state after the power MOSFET receives a signal to switch to the ON state to allow the power MOSFET to switch to the ON state when a drain voltage of the power MOSFET's reaches its lowest value during a switching cycle.

Abstract: A regulating circuit including a first direct current (DC)-DC converter configured to apply a first supply voltage to a first node in a first mode and apply the first supply voltage to a second node in a second mode, a first low drop output (LDO) regulator connected to the first node, the first LDO regulator configured to provide an output voltage to an output node by regulating the first supply voltage of the first node, and a second LDO regulator connected to the first node, the second LDO regulator configured to provide an auxiliary current to the first node in the second mode may be provided.

Abstract: A regulated power supply includes a capacitively isolated feedback circuit and a pulse width modulator (PWM) operable to produce a plurality of pulses at an output and receive a sampled voltage at a feedback input thereof. The capacitively isolated feedback circuit includes a capacitively isolated gate drive circuit directly coupled to the PWM output and configured to produce a plurality of isolated pulses from the plurality of pulses received from the PWM output. The capacitively isolated feedback circuit also includes a forward converter feedback circuit, which includes a switching transistor directly coupled to the capacitively isolated gate drive circuit for receiving the plurality of isolated pulses at a gate of the switching transistor and a feedback transformer directly coupled to the PWM for providing the sampled voltage at the feedback input. The plurality of isolated pulses causes the feedback transformer to sample a load voltage as the sampled voltage.

Abstract: an overvoltage protector for protecting a device to be protected, having a first terminal and a second terminal. A number of strings are connected in parallel to one another between the first terminal and the second terminal, each string having a resistor, and at least one of the strings comprising a switching element that is connected in series to the resistor of the string. A circuit having an overvoltage protector, a use of an overvoltage protector, and a method for operating an overvoltage protector is also provided.

Abstract: A substrate fixing device includes a baseplate, an adhesive layer on the baseplate, and an electrostatic chuck on the adhesive layer. The adhesive layer includes a first layer and a second layer. The second layer is between the first layer and the electrostatic chuck. The thermal conductivity of the first layer is higher in a stacking direction in which the baseplate, the adhesive layer, and the electrostatic chuck are stacked than in a plane direction perpendicular to the stacking direction. The thermal conductivity of the second layer is higher in the plane direction than in the stacking direction.

Abstract: A bandgap voltage generating apparatus and an operation method thereof are provided. The bandgap voltage generating apparatus includes a bandgap circuit, a frequency dividing circuit, and a logic circuit. The bandgap circuit is configured to determine whether to generate a bandgap voltage based on an enable clock. The frequency dividing circuit is configured to divide an original clock to generate at least one divided clock. The logic circuit is coupled to the frequency dividing circuit and the bandgap circuit. The logic circuit uses at least one of the at least one divided clock to generate the enable clock for an enable terminal of the bandgap circuit.

Abstract: An electrostatic discharge (ESD) protection device includes a voltage divider circuit, a detection circuit, and a clamping circuit. The voltage divider circuit outputs N?1 bias voltages according to a first voltage and a second voltage, in which N is a positive integer greater than or equal to 2. The detection circuit detects an ESD event according to a voltage level at a predetermined node associated with the first voltage and the second voltage, and to generate N control signals according to the first voltage, the second voltage, and the N?1 bias voltages. When the ESD event occurs, the voltage level of the N control signals are the same as the first voltage. The clamping circuit is turned on according to the N control signals when the ESD event occurs, in order to provide a discharging path of a current associated with the ESD event.

Abstract: A linear regulator operates in the manner of a linear voltage regulator, but with the functionality of a switching converter. This concept enables DC voltage up-conversion with no switching, more efficient step down of large voltage steps, and requires no expensive and bulky additional components. An optocoupler device transfers power between light emitting and photovoltaic devices.

Abstract: An ESD protection device including a PNP transistor connected to an input pad, a diode connected to the PNP transistor and connected to an output pad, and an NMOS transistor connected to the PNP transistor and the output pad, wherein the diode, PNP transistor, and NMOS transistor are configured to route different levels of an electrostatic discharge (ESD) current pulse from the input pad to the output pad.

Abstract: The disclosure discloses a bus voltage secondary ripple suppression method and a bus voltage secondary ripple suppression device. The method includes: determining a current working mode of an inverter Boost circuit; wherein the working mode includes a continuous current mode (CCM) and a discontinuous current mode (DCM); calculating an output compensation amount according to the current working mode of the inverter Boost circuit; superimposing the output compensation amount on a control output amount of the Boost circuit; and controlling the Boost circuit by a control output amount superimposed with an output compensation amount. According to the scheme of this embodiment, the third harmonic in the output current of the inverter is reduced, and the current output quality of the inverter is improved.

Abstract: A power conversion system includes a first power converter and a second power converter which are capable of converting an alternating-current power into a direct-current power or converting a DC power into an AC power. The first power converter is interconnectable to a first AC system via a first AC circuit breaker. The second power converter is interconnectable to a second AC system via a second AC circuit breaker. A first DC terminal of the first power converter and a second DC terminal of the second power converter are connectable. The first power converter begins operation prior to the second power converter. A first control device controls a voltage of the first DC terminal, based on a status of the second power converter sent from a second control device.

Abstract: A half-bridge electronic device comprises a high level switch and a low level switch in series that are connected at a central point, and a first and a second synchronization system: • the first system comprising a first detection circuit configured to interpret a variation, following a falling edge, of the voltage (Vm) at the central point, and the first system being configured to generate a first synchronization signal (ATON-LS) for activating the low level switch; • the second system comprising a second detection circuit configured to interpret a variation, following a rising edge, of the voltage (Vm) at the central point, and the second system being configured to generate a second synchronization signal (ATON-HS) for activating the high level switch.

Abstract: Controlling an active clamp field effect transistor (FET) in a secondary-controlled active clamp converter is described. In one embodiment, an apparatus includes a primary-side FET coupled to a transformer, a secondary-side FET coupled to the transformer, and an active clamp FET disposed on a primary side of the transformer. A secondary-side controller is configured to control the active clamp FET across a galvanic isolation barrier.

Abstract: A low-power direct current-direct current (DC-DC) converter includes a capacitor, an inductor electrically connected to the capacitor, a first switch configured to be turned on for a first switching interval and supply energy from an input power source to the inductor for the first switching interval, a second switch configured to be turned on for a second switching interval and electrically connect the inductor and a ground terminal for the second switching interval, and a switching control circuit configured to generate first and second switching signals. The switching control circuit is further configured to generate a first sample signal by sampling the voltage level of a first node, and to determine, responding to the first sample signal in time domain, an pulse width adjustment adapted to adjust at least one of the length of a second switching interval and the length of a common blocking interval.

Abstract: A reference voltage generator includes an output terminal, a current source, a reference circuit, a protection circuit, and a control circuit. The output terminal outputs a reference voltage. The current source is coupled to the output terminal, and generates a reference current. The reference circuit is coupled to the output terminal, and generates a reference voltage according to the reference current. The protection circuit is coupled to the output terminal, and adjusts a voltage of the output terminal to an operating voltage. The control circuit is coupled to the reference circuit and the protection circuit. The control circuit controls the reference circuit and the protection circuit according to a start signal.

Abstract: For AC-DC conversion, signal is extracted, then sampled and held and released. Extraction element receives AC signal to generate extracted signal, then sample and hold and release element receives the extracted signal to generate DC signal. Extraction and/or sample and hold and release signal processing may use microprocessor or controller programmably to generate the extracted signal and/or DC signal. Extraction is configurable such that AC signal is received at extraction time or temporal window, whereby said extraction element generates the extracted signal having an extraction current or voltage value during at least one extraction time, and preferably said sample and hold and release element generates the DC signal having the same extraction current or voltage value.

Abstract: A circuit breaker failure protection relay includes an input circuit to which an opening command from a first circuit breaker is input, and a circuit breaker failure detection element configured to compare a magnitude of a current detection signal in a power system with a setting value to make a determination about an overcurrent. The circuit breaker failure detection element is capable of changing the setting value to a first value and a second value that is larger than the first value according to a switching signal. The circuit breaker failure protection relay is configured to, when the opening command is input and when the circuit breaker failure detection element determines that an overcurrent occurs, output an opening command for the second circuit breaker in a neighborhood of the first circuit breaker.

Abstract: Timing circuitry causes: a first closed signal on a first switch control output before a signal on a second switch control output changes from a second closed signal to a first open signal; the first switch control output to provide a second open signal after a first selected time after the second switch control output changes from the second closed signal to the first open signal; and a third switch control output to provide a third closed signal a second selected time after the first switch control output changes from the first closed signal to a third open signal. A beginning of the first closed signal to a beginning of the first open signal is based on a later of: a current through a switch connected to the second switch control output exceeding a threshold current; and a clocked time after the beginning of the first closed signal.

Abstract: Systems and techniques are disclosed that monitor an area adjacent to power system components and detect objects that may pose a probable risk of causing a fault, for example, making contact with the power system component. Various embodiments initiate a preventative, a corrective, and/or a mitigative action in advance of the fault. Examples of possible actions include, but are not limited to, an audible alert, a visual alert, a tactile alert, a remote notification, a limiting of machinery motion, a stopping of machinery motion, a reversing of machinery motion, de-energization of the power system component, or combinations thereof.