Abstract: A method for evaluation of thin film non-uniform stress using high order wafer warpage, the steps including measuring a net wafer warpage across a wafer area due to thin film deposition, fitting a two dimensional low-order polynomial to the wafer warpage measurements and subtracting the low-order polynomial from the net wafer warpage across the wafer area.

Abstract: A vertical memory device including: a circuit pattern on a first substrate; an insulating interlayer on the first substrate, the insulating interlayer covering the circuit pattern; a bending prevention layer on the insulating interlayer, the bending prevention layer extending in a first direction substantially parallel to an upper surface of the first substrate; a second substrate on the bending prevention layer; gate electrodes spaced apart from each other in a second direction on the second substrate, the second direction being substantially perpendicular to the upper surface of the first substrate; and a channel extending through the gate electrodes in the second direction.

Abstract: A method for forming a three-dimensional (3D) memory device includes forming a dielectric stack including a plurality of first/second dielectric layer pairs over a substrate, forming a plurality of channel structures extending in a lateral direction in a core region of the dielectric stack, forming a staircase structure including a plurality of stairs extending along the lateral direction in a staircase region of the dielectric stack, forming a first drain-select-gate (DSG) cut opening extending in the lateral direction in the core region and a second DSG cut opening in the staircase region, and forming a first DSG cut structure in the first DSG cut opening and a second DSG cut structure in the second DSG cut opening.

Abstract: A semiconductor device of the disclosure includes a peripheral circuit structure including a peripheral transistor, a semiconductor layer on the peripheral circuit structure, a source structure on the semiconductor layer, a gate stack structure disposed on the source structure and including insulating patterns and conductive patterns alternately stacked, a memory channel structure electrically connected to the source structure and penetrating the gate stack structure, a support structure penetrating the gate stack structure and the source structure, and an insulating layer covering the gate stack structure, the memory channel structure and the support structure. The support structure includes an outer support layer contacting side walls of the insulating patterns and side walls of the conductive patterns, and a support pattern and an inner support layer contacting an inner side wall of the outer support layer.

Abstract: A semiconductor package including a semiconductor chip, an interposer on the semiconductor chip, and a molding layer covering at least a portion of the semiconductor chip and at least a portion of the interposer may be provided. The interposer includes a interposer substrate and a heat dissipation pattern penetrating the interposer substrate and electrically insulated from the semiconductor chip. The heat dissipation pattern includes a through electrode disposed in the interposer substrate and an upper pad disposed on an upper surface of the interposer substrate and connected to the through electrode. The molding layer covers at least a portion of a sidewall of the upper pad and the upper surface of the interposer substrate. At least a portion of an upper surface of the upper pad is not covered by the molding layer.

Abstract: A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises a cavity therein that comprises a stair-step structure. Sidewalls of the cavity and steps of the stair-step structure are lined with an insulator material. Insulative material is formed in the cavity radially inward of the insulator material. An upper portion of the insulative material is removed from the cavity to leave the insulative material in a bottom of the cavity over the stair-step structure. After the removing, insulating material is formed in the cavity above the insulative material. Other embodiments, including structure independent of method, are disclosed.

Abstract: A method for forming a semiconductor structure for a memory device, including providing a substrate comprising a memory cell region and a peripheral circuit region defined thereon, and the peripheral circuit region comprising at least an active region formed therein, forming at least a buried gate structure in the active region, and an insulating layer being formed on a top of the buried gate structure, and forming a conductive line structure on the buried gate structure, and the conductive line structure and the buried gate structure being physically spaced apart and electrically isolated from each other by the insulating layer.

Abstract: An electronic device includes an object substrate, an electronic unit and an electrostatic discharge protective unit. The object substrate includes a bonding pad. The electronic unit includes an electrode bonding on the bonding pad. The electrostatic discharge protective unit is located in the object substrate and electrically connected to the bonding pad.

Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.

Abstract: Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with increased cell density. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells. Some embodiments form 3D NAND devices with smaller CD memory holes. Some embodiments form 3D NAND devices with silicon layer between alternating oxide and nitride materials.

Abstract: A microelectronic device comprises a stack structure, a stadium structure within the stack structure, a source tier underlying the stack structure, and a masking structure. The stack structure has tiers each comprising a conductive structure and an insulating structure. The stadium structure comprises a forward staircase structure, a reverse staircase structure, and a central region horizontally interposed between the forward staircase structure and the reverse staircase structure. The source tier comprises discrete conductive structures within horizontal boundaries of the central region of the stadium structure and horizontally separated from one another by dielectric material. The masking structure is confined within the horizontal boundaries of the central region of the stadium structure and is vertically interposed between the source tier and the stack structure.

Abstract: A semiconductor memory device is disclosed. The device includes a peripheral circuit structure on a substrate, a semiconductor layer on the peripheral circuit structure, an electrode structure on the semiconductor layer, the electrode structure including electrodes stacked on the semiconductor layer, a vertical channel structure penetrating the electrode structure and being connected to the semiconductor layer, a separation structure penetrating the electrode structure, extending in a first direction, and horizontally dividing the electrode of the electrode structure into a pair of electrodes, an interlayered insulating layer covering the electrode structure, and a through contact penetrating the interlayered insulating layer and being electrically connected to the peripheral circuit structure.

Abstract: According to one embodiment, a semiconductor device includes: a first well region of N-type and a second well region of P-type; a PMOS transistor provided in the first well region; and an NMOS transistor provided in the second well region. The PMOS transistor includes a first gate insulating layer and a first gate electrode. The NMOS transistor includes a second gate insulating layer and a second gate electrode. The first gate electrode includes a first semiconductor layer of P-type, a first insulating layer, and a first conductive layer. The second gate electrode includes a second semiconductor layer of N-type, a second insulating layer, and a second conductive layer. A film thickness of the first insulating layer is thicker than a film thickness of the second insulating layer.

Abstract: A memory device includes a lower structure, a stacked structure on the lower structure, the stacked structure including horizontal layers and interlayer insulating layers alternately stacked in a vertical direction, and each of the horizontal layers including a gate electrode, a vertical structure penetrating through the stacked structure in the vertical direction, the vertical structure having a core region, a pad pattern with a pad metal pattern on the core region, a dielectric structure including a first portion facing a side surface of the core region, a second portion facing at least a portion of a side surface of the pad metal pattern, and a data storage layer, and a channel layer between the dielectric structure and the core region, a contact structure on the vertical structure, and a conductive line on the contact structure.

Abstract: Some embodiments relate to a semiconductor structure. The semiconductor structure includes a conductive structure over a semiconductor substrate. A first dielectric layer is over the conductive structure. A second dielectric layer is over the first dielectric layer. An interconnect structure is over the conductive structure and disposed in the first and second dielectric layers. The interconnect structure has a protrusion in direct contact with a sidewall of the conductive structure. The interconnect structure comprises an interconnect liner surrounding a conductive interconnect body. A sidewall spacer is disposed on the sidewall of the conductive structure.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers comprising laterally-spaced memory-block regions having horizontally-elongated trenches there-between. Two of the first tiers have different vertical thicknesses relative one another. Channel-material strings of memory cells extend through the first tiers and the second tiers. Through the horizontally-elongated trenches, first conductive material is formed in void space in the two first tiers. The first conductive material fills the first tier of the two first tiers that has a smaller of the different vertical thicknesses in individual of the memory-block regions. The first conductive material less-than-fills the first tier of the two first tiers that has a larger of the different vertical thicknesses in the individual memory-block regions.

Abstract: A semiconductor device includes a stacked film of electrode layers and insulating layers. A charge storage layer is in a hole in the stacked film on a first insulating film. A channel layer is on the charge storage layer via a second insulating film. An adsorption promoting layer is on surfaces of a third insulating layer covering the insulating layers and the first insulating film facing the electrode layers. The third insulating film includes a first metal element and a first element, and the adsorption promoting layer includes a second element and a third element. The difference in electronegativity between the second element and the third element is larger than a difference in electronegativity between the first metal element and the first element.

Abstract: A semiconductor device includes; gate layers stacked on a substrate, a channel layer extending through the gate layers, a string select gate layer disposed on the channel layer and a string select channel layer extending through the string select gate layer to contact the channel layer. The string select channel layer includes a first portion below the string select gate layer including a first protruding region, a second portion extending through the string select gate layer, and a third portion above the string select gate layer including a second protruding region.

Abstract: Techniques are disclosed for methods of post-treating an etch stop or a passivation layer in a thin film transistor to increase the stability behavior of the thin film transistor.

Abstract: A three-dimensional flash memory is provided, and technique to suppress interference caused by an inter-cell insulation layer in a vertical cell and to form a stable vertical channel layer, a technique to reduce a length of wire than a conventional three-dimensional flash memory for overcoming problems of deterioration of chip characteristics such as operation speed and power consumption and difficulty of wiring technique in the manufacturing process, and a technique to improve horizontal density of channel layers and ONO layers are proposed.