Abstract: A memory system including a circuit for switching control of a read-only memory and a random-access memory to allocate addresses thereto. The addresses are switched between the read-only memory and the random-access memory by selecting a mode in which the read-only memory is operated when reading therefrom and the random-access memory is operated when writing thereinto, and a mode in which the random-access memory is operated when reading therefrom and writing thereinto.

Abstract: A semiconductor memory device used as a bipolar random access memory including a plurality of pairs of word lines, a plurality of pairs of bit lines, and a plurality of static memory cells located at the intersections of and connected between the pairs of word and bit lines. A plurality of constant current sources are selectively connected to the bit lines. A reading-writing voltage control circuit controls the potential of each bit line during the reading and writing of data and a writing current control circuit controls the current flowing to each bit line during the writing of data into the memory cell. Further, the writing current control circuit connects the constant current source to the reading-writing voltage control circuit in the writing of data to the memory cell. Accordingly, the bipolar random access memory can operate at a high speed with reduced power consumption and without unnecessary current flowing in the peripheral circuits.

Abstract: A memory arrangement for temporary data storage of the FIFO type includes a random access memory associated with an input buffer register and two output buffer registers. The registers may consist of transparent flip-flops. The control system for the arrangement is provided for authorizing reading out from the output register at any time independently of the writing times in the random access memory and for causing reading out from the random access memory in response to an indication that the first output register is empty. A priority input of said control system makes it possible to interrupt a reading or writing operation when a request for the other operation is received. The control system has means for detecting full condition and empty condition of the FIFO. The control system further includes a handling logic for the output registers.

Abstract: A static memory circuit includes memory cells arranged in a matrix of word lines and bit lines, and a reset circuit for resetting each pair of bit lines to have an equivalent potential in response to a change in a row address signal. The reset circuit generates a reset signal at a first time a certain time period after a first change of the row address signal and terminates the reset signal at a second time when a second change of the row address signal is detected. Thus, data destruction during reading is prevented.

Abstract: A redundancy circuit that consumes no power before or after activation switches a pair of output nodes from a first set of complementary logic levels to an inverted set when it is activated by blowing a pair of fuses.

Abstract: A semiconductor memory device has a memory circuit with a plurality of memory cells, a data transmission line for transmitting the data from the memory circuit, and a data detection circuit for detecting the memory data supplied through the data transmission line. The data detection circuit produces output data in accordance with the direction of change in logic level of the memory data supplied through the data transmission line.

Abstract: A dynamic type semiconductor memory device includes a memory cell having a capacitor for storing an amount of charge corresponding to data and, an n-channel MOS transistor to control charging and discharging to and from the capacitor, and a control unit to permit a read/write operation of the memory cell. The control unit of the memory device includes a drive circuit for generating turn on and turn off voltages, a charge pump circuit connected to the gate of the memory cell, and a switching element connected between the drive circuit and the gate of the MOS transistor.

Abstract: An on-chip apparatus for generation of timing signals for a large scale integrated (LSI) chip or semiconductor memory array is disclosed. This apparatus may be used both during the production testing of the memory and during normal functional operation. In the testing environment it allows use of much less expensive peripheral test equipment, while also providing for much greater accuracy in determination of whether or not the memory array meets its timing specification. Use during normal functional operation (subsequent to use in the test environment) provides for a guarantee of defect free operation.

Abstract: A sense amplifier comprising two asymmetrical differential amplifiers connected to each other in such a way that their outputs are accelerated to charge up one another by utilizing nodes at which potentials are changed in response to a change of the input signal supplied from a pair of bit lines or a pair of data lines, whereby the operating speed of the sense amplifier is increased.

Abstract: An output circuit for a semiconductor memory device including a preset circuit connected to a data output terminal and adapted to set a potential on the data output terminal to a potential between a potential of a first potential supply terminal and a potential of a second supply terminal during a preparative period for read preceding a data readout from a memory cell whereby the potential level on the data output terminal reaches a "H" level or a "L" level. Thus, the output circuit with high speed readout operation and with high reliability by means of being free from the instability caused by an output noise can be obtained.

Abstract: A redundant column circuit includes a row shared predecoder (12) and predecoders (16), (18) and (20). The predecoders (16-20) are input to a one-of-sixty-four decoder (28) for providing sixty-four decoded outputs therefrom, each of which is input to a one-of-four multiplexer (30). Each of the multiplexers (30) selects one of four normal decode outputs and one of four redundant decode outputs. The selected decode output is determined by the four outputs from the row shared predecoder (12). A switch bank (32) of single pole double throw switches selects between a normal and a redundant output with the redundant output having the address associated therewith incremented by one. The output of the switches in the bank (32) is input to the deactivation circuits (36) for output therefrom to a memory array (38). The memory array (38) has a redundant column (R) in parallel therewith which is controlled by the first switch in a the switch bank (32).

Abstract: A dynamic semiconductor memory device comprising: (1) one-transistor one-capacitor type memory cells connected between word lines and bit lines and (2) flip-flops, each flip-flop being connected between a pair of word lines to clamp an unselected word line in the pair of word lines to the low voltage of a power source, thereby preventing a subsequent erroneous reading operation as a result of an increase in potential of the unselected word line.

Abstract: A device is disclosed for securely housing and protecting microelectronic circuitry in order to prevent external access to sensitive data stored therein. In a preferred embodiment of the invention, the device includes a ceramic housing which encases electronic circuitry. The ceramic housing is comprised of a plurality of individual parts selectively connected together, with each of the parts being comprised of a ceramic substrate and a plurality of ceramic layers disposed thereon. The electronic circuitry includes a memory for storing sensitive data therein and a tamper detection circuit. The tamper detection circuit includes a conductive path selectively provided through the plurality of ceramic layers of each of the plurality of individual parts and is responsive to any attempt to penetrate the ceramic housing which damages the conductive path for clearing the memory of any sensitive data stored therein.