Abstract: A debug system generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device for used in electronic design automation (EDA). The FPGA device (Behavior Processor) operates to execute in hardware code constructs previously executed in software. When some condition is satisfied (e.g. If . . . then . . . else loop) requiring intervention, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response. A memory block from a logic device is mapped to a memory device in a re-configurable hardware unit using a memory mapping system including a conductive connector driver, a memory block interface, and evaluation logic in each logic device, the connector driver, the interface, and the connector controller, the evaluation logic providing control signals used to evaluate data in the hardware model and to control write/read memory access between the logic device and the memory device via the driver and interface.

Abstract: A command queue is maintained in a disk drive. The command queue includes a plurality of access commands that are awaiting execution. The command queue is sorted to provisionally select one of the plurality of access commands as the next command to be executed. A seek start deadline is calculated for the provisionally selected access command based on an estimated extra latency of the provisionally selected access command. A seek operation with respect to the provisionally selected access command is deferred based on the calculated seek start deadline, to await arrival at the disk drive of a new access command. If the new access command arrives at the disk drive prior to the seek start deadline, the respective estimated access times for the provisionally selected access command and the newly arrived access command are compared to select one of the two access commands for execution.

Abstract: A computer system includes a read ahead engine that receives a sequence of read requests and performs read ahead operations in accordance with various patterns detected within the sequence of read requests. The prefetch engine may implement the method of storing a first run value indicative of the run size of a first plurality of sequential read requests, and storing a first skip value indicative of a non-sequential skip associated with a subsequent read request. The method may further include determining whether a second run value indicative of the sequential run size of a second plurality of read requests equals the first run value, and whether a second skip value indicative of another non-sequential skip associated with an additional read request equals the first skip value. If the first run value equals the second run value, and the first skip value equals the second skip value, a stride pattern is indicated, and one or more read ahead operations according to the detected stride pattern may be initiated.

Abstract: A method, which may be embodied upon a computer readable medium and executed by a processor, for dynamically adjusting engine startup parameters for a hard disk drive system. The method includes determining if a drive catch-up condition or a host catch-up condition has occurred and adjusting at least one of a read pad and a write pad if a drive catch-up condition is determined. The method further calculating a pad parameter and an optimal delay parameter if a host catch-up condition is determined. Thereafter, the method includes adjusting the optimal delay parameter with the pad parameter if a host catch-up condition is determined.

Abstract: Method and apparatus for storing and retrieving copy-protected data within storage devices such as, for example, disc drives. Data that is to be copy protected is written on the storage device. A first data list, such as a manufacturer's storage device defect list, is copied and used to make a second data list. Then, the first data list is modified such that the area where the copy protected data is stored is identified as defective. Unless a request to read the copy protected data is received, the first data list is used and the copy protected data area is considered defective. However, if a request to read the copy protected data is received, the second data list is used and the copy protected data is read from its storage location.

Abstract: In the address translation, there is a region in which the translation having a common regularity is possible into a plurality of regions, and a region in which such a translation is not possible. An address translation circuit is disposed between a master circuit and a slave circuit. The address translation to the former region is performed by a first address translation system in which the translated address is produced by a manipulation including permutation of a part of the original address, and the address translation to the latter region is performed by a second address translation system in which a part of the original address is replaced with translated address information stored beforehand. The data processor includes the address translation circuit having both of the first and second address translation systems.

Abstract: A system (10) implements user programmable addressing modes in response to control information contained within an input address. Encoded control information stored in a plurality of user programmed address permutation control registers (70-72) is used to determine what bit values are used to replace predetermined bits of the input address to selectively create a corresponding permutated address. Since no modification to a processor's pipeline is required, various permutation addressing modes may be user-defined and implemented using either a general-purpose processor or a specialized processor.

Abstract: A cache memory system includes a tag RAM storing tags in a plurality of sets thereof, a data RAM storing data in a plurality of sets corresponding to the tag RAM sets, and a control logic controlling overall functions in the cache memory. The control logic generates set selection signals which designate the sets storing data replaceable with those of the data RAM in accordance with N-bit data representing a replacement condition of data stored in the data RAM sets. The control logic is composed of counters generating the set selection signals synchronous with a predetermined clock signal in order to modify the sets replaceable data in a random order, so that block replacement logic is constructed in a more simplified form though the number of sets increases in a set-associative cache memory.

Abstract: When storage controllers are added to a storage system to change the storage system from a configuration having only one storage controller to a configuration having plural storage controllers, or when storage controllers are removed from the storage system to change the storage system from a configuration having plural storage controllers to a configuration having only one storage controller, a controller-internal management-information memory controller carries out a copy process to copy management information from each of the storage controllers to a management-information-memory switch or vice versa at the same time as processing of read and write requests for access to the management information, made by a channel interface or a disc interface, in order to change storage locations of the management information while processing the read and write requests made by the host.

Abstract: A method and apparatus for a source synchronous address receiver for a system bus is described. A flow-through between a system bus address input to a memory bus is controlled by two inputs: one is a source synchronous address strobe directing the receiver to latch the address and store data, while the other is a protocol signal, signaling the beginning of the address transfer. A flow-through circuit generates an enable signal in response to a digital address strobe signal and a digital address select signal to generate, prior to receipt of the address packet, an enable signal for a flow-through gate having the address packet and the enable signal as inputs. The flow-through gate provides the first component of the digital address packet (transaction address) to a chipset once the digital address packet appears on the address pin.