Abstract: A bipolar stimulation probe including a first electrode, a second electrode, a control module, and switches. The control module is configured to stimulate nerve tissue of a patient by generating (i) a first output signal indicative of a first pulse to be output from the first electrode, and (ii) a second output signal indicative of a second pulse to be output from the second electrode. The first pulse and the second pulse are monophasic. The switches are configured to output from the bipolar stimulation probe (i) the first pulse on the first electrode based on the first output signal, and (ii) the second pulse on the second electrode based on the second output signal.

Abstract: This application provides a communication method and a communications apparatus. The method includes: in a process in which a terminal device performs beam failure recovery in a first bandwidth, determining, by the terminal device, that an operating bandwidth needs to be switched from the first bandwidth to a second bandwidth; and switching, by the terminal device, from the first bandwidth to the second bandwidth according to a preset policy. According to embodiments of this application, the operating bandwidth can be switched in the beam failure recovery process.

Abstract: Methods and apparatus for facilitating the deployment of a wireless extender in combination with a base station at a customer premises are described. Support is provided for data rate testing in combination with configuring one or more aspects of the system such as wireless extender and/or base station transmission power level. By using testing a system can be deployed where one or more devices may use transmission power levels which are less than the maximum permitted transmission power level while still supporting an expected data rate corresponding to a subscriber service level in a reliable manner. In various embodiments DFS channel black and/or white lists are generated for each link taking into consideration the determined transmit power to be used for a given link.

Abstract: An memory device, and method of making same, that includes source and drain regions defining a channel region therebetween. A select gate is formed over and insulated from a first portion of the channel region. A conductive floating gate is disposed over and insulated from the source region and a second portion of the channel region. A notch is formed in the floating gate bottom surface having an edge that is either aligned with an edge of the source region or is disposed over the source region. A conductive control gate is disposed adjacent to the floating gate. By having the source region terminate under the thicker insulation region provided by the notch, the breakdown voltage of the source junction is increased. Alternately, the lower portion of the floating gate is formed entirely over the source region, for producing fringing fields to control the adjacent portion of the channel region.

Abstract: A connection condition between two adjacent original surfaces, selected from a plurality of connected original surfaces, is determined as to whether it is smooth, concave, or convex. Then, each of the original surfaces is offset at a predetermined distance along unit vectors normal to the original surface, to obtain an offset surface. Also, an original loop for each of the original surfaces is offset at the predetermined distance along unit vectors normal to the original surface at its edges to obtain an offset loop. Then, a new surface between two adjacent offset loops is interpolated when the connection condition is convex. A self-interference portion is removed when the connection condition is concave, so as to obtain a plurality of offset surfaces based on the plurality of original surfaces.

Abstract: A high performance computer graphics image computation system architecture is disclosed. The system architecture includes a computational processor ring which includes a plurality of closely coupled computational subsystems. The computational subsystems operate asynchronously and each is interconnected with two adjacent computational subsystems. The architecture of the processor ring allows rapid communication between the computational subsystems while avoiding a deadlock condition. The system architecture also includes a video processor ring wherein a plurality of video processors are synchronously linked together. A plurality of local communication paths couple the computational subsystems to the video processors. The video processor ring is able to move massive amounts of data, in the form of digital video signals, from various points within the system.

Abstract: A computer input system for Chinese and Japanese characters. The different strokes for composing the characters are classified into different groups, each identified by a code number. The strings of code numbers are stored in memory where the strings contain only as many code numbers as are necessary to identify the characters. Strings for two or more characters used together as compounds are also stored. When a code number entered by an operator matches a string stored, a controller causes the shape of the actual character to be fetched from memory and displayed. For some characters, partial characters are also stored and are fetched and displayed when the string of code numbers for such partial characters matches the code numbers entered to aid beginners. The string of code numbers representing each character follows exactly a traditional; writing sequence of the character from the very first stroke to the end of the string of code numbers.

Abstract: An electronic apparatus includes a program memory having a parallel transfer program and a serial transfer program, a connector on the electronic apparatus to which a parallel transfer interface or a serial transfer interface is detachably connected, and a judging unit for judging the kind of the printer interface connected to the connector. A program suitable for the kind of the printer interface judged by the judge unit is called from the program memory by means of a program selecting unit. This enables the electronic apparatus to be connected for use with a parallel transfer printer and a serial transfer printer.

Abstract: In sequential processings of converting input picture data springs having unitary picture data in succession to picture data of a form adapted for displaying, storing the resultant picture data and then displaying the same in a display, a first detection data and a second detection data are monitored. The first detection data is indicative of commencement of the unitary picture data and is detected from the input picture data strings. The second detection data is indicative of termination of the conversion and is detected on the unitary picture data basis. If the second detection data has not been detected at the time when the first detection data has been detected, the unitary picture data detected with the first detection data is invalidated and the unitary picture data is left unprocessed.

Abstract: A graphics system uses a programmable tile size and shape supported by a frame buffer memory organization wherein (X, Y) pixel map into regularly offset permutations on groups of RAM (Random Access Memory) address and data line assignments. Changing the mapping of (X, Y) pixel addressed to RAM addresses for the groups changes the size and shape of the tiles. A pixel data/partial address multiplexing method based on programmable tile size reduces the number of interconnections between a pixel interpolator and the frame buffer without significantly increasing the number of bus cycles needed to transfer the information. A programmable pipelined shifter allows the dynamic alteration of the mapping between bits of the RGB (red, green, blue) intensity values and the planes of the frame buffer into which those bits are stored, as well as allowing those values to be truncated to specified lengths. Tiles are cached. Tiles for RGB pixel values are cached in an RGB cache, while Z values are cached in a separate cache.

Abstract: A printer for printing bit images in accordance with printing information and control information which includes a detector for detecting when a print engine enters a predetermined state such as an abnormal state. A memory stores data relating to at least one page of bit images being printed at the time the predetermined state is entered. When the printing engine recovers from the predetermined state, the data stored in the memory are read out to immediately restart the printing operation.

Abstract: A TV data capture device is used with a TV set or monitor to selectively extract, store, retrieve and display on the TV set or monitor extracted digital data. A composite video-digital signal is received from which digital data is removed by a digital data extractor. A memory unit, a permanent storage unit, and a microprocessor are also provided, enabling the user to store and retrieve from storage selected digital data previously extracted from the composite signal. A digital video converter converts extracted digital data to video signals for display of extracted digital data with the currently transmitted video signal.

Abstract: A raster image processor for an all points addressable marking engine includes a page memory having a data input and a write enable input. Halftone tints are applied to bit maps of objects stored in the page memory by applying a tint bit pattern to the data input of the page memory while a bit pattern representing the object is being applied to the write enable input of the page memory. Prior to applying the object bit maps to the write enable input of the page memory, the object bit maps may be combined with a texture bit pattern or clipped by a window bit pattern.

Abstract: A method for clip checking three dimensional images for display on a computer display system. The display system includes a computer having a central processing unit(CPU) coupled to a memory and a cathode ray tube (CRT) display. The method of the present invention includes inputting a plurality of points comprising an image to be displayed, wherein each of the points is described by X,Y,Z and W world coordinates. The points are stored in the memory coupled to the CPU. The CPU executes a viewing algorithm which transforms the world coordinates for each point into view reference coordinates. The view reference coordinates have an origin at the viewpoint of the user, with the Z axis pointed outward in the direction of the display screen. Each of the points of the image are described by clipping bits X Right, X Left, Y Top, Y Bottom, Z Back, and Z Front. The view reference coordinate system permits the user to selectively enable/disable clipping quadrants in X,Y,Z and W space.

Abstract: The two-digit number displayed by a display apparatus (1) is adjusted by means of a microcontroller (4) in response to actuation of increment (5) and decrement (6) keys. Each new actuation of the increment key results in incrementation of the displayed number by unity. However, if this actuation is prolonged the first number in each succeeding higher ranking decade are next displayed in direct succession. Similarly, each new actuation of the decrement key results in decrementation of the displayed number of unity. However, if this actuation is prolonged the first number of the current decade and then the first number of each decade of successively lower rank are next displayed in direct succession.

Abstract: Methods and apparatus for scanning and vectorizing artwork in which a grid is applied to photoplot artwork. Preferably the grid is automatically created from the scanned image of the artwork using the centerline of each line and the center of each pad in the artwork. The methods and apparatus also determine the rotation or skew of the artwork and adjust the image to compensate for any skew that is found. Grid spacing is determined from frequency plots of the artwork which show the number of lines and points that appear in each row of pixels and in each column of pixels. Fourier analyses of the frequency plots give the grid spacing.

Abstract: In a line generator and a method for determining the individual pixels to be plotted for a line to be drawn in a display system, coded representations of a plurality of lines are stored in a line definition table. The coded representation of each individual line is a string of data items representing the transitions between adjacent pixels to be plotted for drawing the individual line. Preferably, only coded representations of lines up to a predetermined size (i.e. the length of the line in the case of a straight line) are stored in the line definition table. Strings of data items for representing the pixels to be plotted for longer lines to be drawn are still calculated as in the prior art. In this case, control logic determines whether there are coded representations of a line to be drawn in the line definition table, or not, and passes control to appropriate processing logic for determining the pixels to be plotted.

Abstract: A display system includes a memory device, a central processing unit, a converting circuit and a display device. The memory device is for sequentially storing image data at addresses corresponding to positions in line and column directions of an original image to be displayed. The central processing unit controls the overall operation of the system and also retrieves the image data selectably either from every line or every Mth line. The converting circuit sequentially and temporarily stores the retrieved image data by extracting selectably either every bit or every Nth bit of the retrieved image data sequentially, M and N being integers greater than 1. These serial data formed by the converting circuit are displayed by the display device.

Abstract: An image processor including a memory for storing bit images of a graphic pattern or a character, a receiver for receiving information regarding an image to be outputted from an external apparatus, and an image writer for writing bit images on the memory in accordance with the received information. A timer is provided and starts to clock when the image writer begins to write bit images. A control circuit is also provided for forcibly stopping the operation of the image writer if the imaging operation by the image writer has not yet been completed upon the timer reaching or exceeding a predetermined period. The predetermined time period is determined in accordance with the bit images being a graphic pattern or a character.

Abstract: A control apparatus for controlling a printer in which a memory for memorizing data to be printed is sent from an external processor and a capability for deleting data memorized in the memory is provided. Data in memory is deleted according to a control code sent from the external data processor or entered through an operation panel. A range of data to be deleted is determined based on a control code given.