Patents Examined by Hai Q Pham
  • Patent number: 8000138
    Abstract: A non-volatile scalable memory circuit is described, including a bus formed on a substrate that includes active circuitry, metallization layers, and a plurality of high density third dimension memory arrays formed over the substrate. Each memory circuit can include an embedded controller for controlling data access to the memory arrays and optionally a control node that allows data access to be controlled by an external memory controller or by the embedded controller. The memory circuits can be chained together to increase memory capacity. The memory arrays can be two-terminal cross-point arrays that may be stacked upon one another.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: August 16, 2011
    Inventor: Robert Norman
  • Patent number: 7944760
    Abstract: An electronic circuitry is provided for reading out a memory element (ME). The electronic circuitry comprises a first electronic path (IP) being coupled to the memory element (ME), a second electronic path (RP) having predetermined electrical properties, and a basic detection element (BDE) being coupled to the first and second electronic paths (IP, RP) such that the information contained in the memory element (ME) can be determined by the basic detection element (BDE) based on the relation of a digital signal being propagated over the first path (IP) to a digital signal being propagated over the second path (RP).
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: May 17, 2011
    Assignee: NXP B.V.
    Inventor: Cedric Mayor
  • Patent number: 7920402
    Abstract: A resistance variable memory apparatus (100) of the present invention is a resistance variable memory apparatus (100) using a resistance variable element (22) transitioning between plural resistance states in response to electric pulses of the same polarity, in which a series resistance setting unit (10) is configured to set a resistance value of the series current path and a parallel resistance setting unit (30) is configured to set a resistance value of a parallel current path such that the resistance values become resistance values at which a node potential is not larger than a second voltage level in a state where an electric pulse application device (50) is outputting a first electric pulse after the resistance variable element (22) has switched to the high-resistance state, and the node potential is not larger than a first voltage level in the state where the electric pulse application device (50) is outputting a second electric pulse after the resistance variable element (22) has switched to the low-re
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: April 5, 2011
    Assignee: Panasonic Corporation
    Inventors: Yoshikazu Katoh, Kazuhiko Shimakawa, Zhiqiang Wei