Patents Examined by Hajar Kolahdouzan
  • Patent number: 12159956
    Abstract: Provided is an optoelectronic semiconductor chip including a semiconductor layer sequence having an active layer, a doped current spreading layer and an output coupling layer, which are arranged one above the other in this order. The active layer generates primary radiation during intended operation. The current spreading layer includes a larger lateral electrical conductivity than the output coupling layer. The output coupling layer includes output coupling structures for coupling out radiation on an exit side facing away from the active layer. The output coupling layer includes a lower absorption coefficient for primary radiation than the current spreading layer.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: December 3, 2024
    Assignee: OSRAM OLED GMBH
    Inventors: Sebastian Pickel, Katharina Werner, Bernd Böhm, Anna Strozecka-Assig, Anna Nirschl
  • Patent number: 12156488
    Abstract: A method includes providing a substrate having a main surface, forming a layer of thermally insulating material on the main surface, forming strips of phase change material on the layer of thermally insulating material such that strips of phase change material are separated from the main surface by thermally insulating material, forming first and second RF terminals on the main surface that are laterally spaced apart from one another and connected to the strips of phase change material, and forming a heater structure having heating elements that are configured to control a conductive connection between the first and second RF terminals by applying heat to the one or more strips of phase change material, wherein each of the strips of phase change material includes multiple outer faces, and wherein portions of both outer faces from the strips of phase change material are disposed against one of the heating elements.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: November 26, 2024
    Assignee: Infineon Technologies AG
    Inventors: Dominik Heiss, Martin Bartels, Christoph Glacer, Christoph Kadow, Matthias Markert, Hans Taddiken, Hans-Dieter Wohlmuth
  • Patent number: 12142647
    Abstract: A method of forming a semiconductor including forming a source/drain feature adjacent to a semiconductor layer stack disposed over a substrate. The method further includes forming a dummy fin adjacent to the source/drain feature and adjacent to the semiconductor layer stack. The method further includes performing an etching process from a backside of the substrate to remove a first portion of the dummy fin adjacent to the source/drain feature, thereby forming a first trench in the dummy fin, where the first trench extends from the dummy fin to the source/drain feature. The method further includes forming a first dielectric layer in the first trench and replacing a second portion of the dummy fin with a source/drain contact.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Han Fan, Wei-Yang Lee, Tzu-Hua Chiu, Chia-Pin Lin
  • Patent number: 12108604
    Abstract: Embodiments of the present disclosure provide an apparatus and methods for forming stair-like structures with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, an opening formed in the film stack, wherein the opening is filled with a channel layer and a center filling layer, and a protective liner layer disposed between the conductive structure and the channel layer.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: October 1, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Jaesoo Ahn, Thomas Kwon, Mahendra Pakala
  • Patent number: 12096705
    Abstract: A memory cell may include an active electrode, an inert electrode, and a dielectric positioned between them. A forward electrical bias between the electrodes may result in the formation of a conductive bridge between them. A reverse electrical bias may result in the dissolution of the conductive bridge. The memory cell may include nanotube structures formed within the dielectric, where the nanotube structures define columns between the active electrode and the inert electrode. A memory device may include multiple such conductive bridge memory cells. A method of forming a memory cell may include positioning an active electrode onto a substrate, positioning a dielectric layer onto the active electrode, forming nanotube structures within the dielectric layer while positioning the dielectric layer, where the nanotube structures define columns within the dielectric layer, and positioning an inert electrode onto the dielectric layer.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: September 17, 2024
    Assignee: Bosie State University
    Inventors: Maria Mitkova, Muhammad Rizwan Latif
  • Patent number: 12063873
    Abstract: A tunnel barrier layer includes a non-magnetic oxide, wherein a crystal structure of the tunnel barrier layer includes both an ordered spinel structure and a disordered spinel structure.
    Type: Grant
    Filed: January 13, 2023
    Date of Patent: August 13, 2024
    Assignee: TDK CORPORATION
    Inventors: Shinto Ichikawa, Katsuyuki Nakada
  • Patent number: 12062738
    Abstract: The invention described herein provides a method and apparatus to realize incorporation of Beryllium followed by activation to realize p-type materials of lower resistivity than is possible with Magnesium. Lower contact resistances and more effective electron confinement results from the higher hole concentrations made possible with this invention. The result is a higher efficiency GaN-based LED with higher current handling capability resulting in a brighter device of the same area.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: August 13, 2024
    Assignee: POWER INTEGRATIONS, INC.
    Inventors: James R. Shealy, Richard J. Brown
  • Patent number: 12057400
    Abstract: Some embodiments include an integrated assembly having a stack of alternating first and second levels. A panel extends through the stack. The first levels have proximal regions adjacent the panel, and have distal regions further from the panel than the proximal regions. The distal regions have first conductive structures, and the proximal regions have second conductive structures. Detectable interfaces are present where the first conductive structures join to the second conductive structures. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: August 6, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Shyam Surthi
  • Patent number: 12046699
    Abstract: The invention described herein provides a method and apparatus to realize incorporation of Beryllium followed by activation to realize p-type materials of lower resistivity than is possible with Magnesium. Lower contact resistances and more effective electron confinement results from the higher hole concentrations made possible with this invention. The result is a higher efficiency GaN-based LED with higher current handling capability resulting in a brighter device of the same area.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: July 23, 2024
    Assignee: POWER INTEGRATIONS, INC.
    Inventors: James R. Shealy, Richard J. Brown
  • Patent number: 12046700
    Abstract: Provided is a nanorod light-emitting device including a first semiconductor layer doped with a first conductive type impurity, an emission layer disposed above the first semiconductor layer, a second semiconductor layer disposed above the emission layer and doped with a second conductive type impurity that is electrically opposite to the first conductive type impurity, a conductive layer disposed between at least one of a center portion of a lower surface of the emission layer and the first semiconductor layer and a center portion of an upper surface of the emission layer and the second semiconductor layer, and a current blocking layer surrounding a sidewall of the conductive layer.
    Type: Grant
    Filed: August 25, 2023
    Date of Patent: July 23, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junhee Choi, Nakhyun Kim, Jinjoo Park, Joohun Han
  • Patent number: 12046625
    Abstract: Provided are a light-emitting element, a manufacturing method thereof, and a display device comprising the light-emitting element. The method for manufacturing the light-emitting element comprises the steps of: preparing a lower substrate including a substrate and a buffer material layer formed on the substrate, forming a separating layer disposed on the lower substrate and including at least one graphene layer, forming an element deposition structure by depositing a first conductivity type semiconductor layer, an active material layer, and a second conductivity type semiconductor layer on the separating layer, forming an element rod by etching the element deposition structure and the separating layer in a vertical direction; and separating the element rod from the lower substrate to form a light emitting element.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: July 23, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jung Hong Min, Dae Hyun Kim, Hyun Min Cho, Dong Uk Kim, Dong Eon Lee, Seung A Lee, Hyung Rae Cha
  • Patent number: 12046480
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor die and surrounding a sidewall of the semiconductor die with a dielectric material. The method further includes forming a post passivation interconnect (PPI) over the semiconductor die and electrically coupling the PPI with the semiconductor die. The method further includes molding the semiconductor die and the PPI into an integrated semiconductor package. The method further includes covering at least a portion of an outer surface of the integrated semiconductor package with a conductive layer, wherein the conductive layer is conformal to the morphology of the portion of the outer surface. Moreover, the method further includes forming a conductive path inside the integrated semiconductor package electrically coupled to the conductive layer and a ground terminal of the integrated semiconductor package.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shou Zen Chang, Chun-Lin Lu, Kai-Chiang Wu, Ching-Feng Yang, Vincent Chen, Chuei-Tang Wang, Yen-Ping Wang, Hsien-Wei Chen, Wei-Ting Lin
  • Patent number: 12048258
    Abstract: A phase change memory device includes a first electrode, a second electrode, a phase change region, a first spacer and a second spacer. The second electrode is disposed over the first electrode. The phase change region is disposed between the first and second electrodes. The first spacer laterally covers the phase change region. The second spacer laterally covers the first spacer, and has a thermal conductivity smaller than that of the first spacer.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Tai Tseng, Chang-Chih Huang, Kuo-Chyuan Tzeng
  • Patent number: 12033992
    Abstract: A package includes a first die, a second die, a bridge structure, a first redistribution structure, and an encapsulant. The first die and the second die are disposed side by side. The bridge structure is disposed over the first die and the second die. The bridge structure includes a plurality of routing patterns and a plurality of connectors disposed on the plurality of routing patterns. The first redistribution structure is sandwiched between the first die and the bridge structure and is sandwiched between the second die and the bridge structure. The plurality of connectors of the bridge structure is in physical contact with the first redistribution structure. The encapsulant encapsulates the bridge structure. The plurality of routing patterns and the plurality of connectors of the bridge structure are completely spaced apart from the encapsulant.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: July 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin, Sheng-Chieh Yang
  • Patent number: 12029049
    Abstract: A memory device includes a substrate, an electrical channel layer, a first electrode, a resistive switching layer, a second electrode, and a conductive structure. The electrical channel layer is disposed on the substrate. The first electrode is disposed on the substrate and extends into the electrical channel layer. The resistive switching layer is disposed between the first electrode and the electrical channel layer. The second electrode is disposed on the electrical channel layer. The conductive structure connects the electrical channel layer and the second electrode.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: July 2, 2024
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Po-Yen Hsu, Bo-Lun Wu, Tse-Mian Kuo, Wei-Che Chang, Shuo-Che Chang
  • Patent number: 12029143
    Abstract: A memory device and a programming method of the memory device are provided. The memory device includes a bottom electrode, a heater, a phase change layer and a top electrode. The heater is disposed on the bottom electrode, and includes heat conducting materials different from one another in terms of electrical resistivity. A first one of the heat conducting materials has a periphery wall portion and a bottom plate portion connected to and surrounded by the periphery wall portion. A second one of the heat conducting materials is disposed on the bottom plate portion of the first one of the heat conducting materials, and laterally surrounded by the periphery wall portion of the first one of the heat conducting materials. The phase change layer is disposed on the heater and in contact with the heat conducting materials. The top electrode is disposed on the phase change layer.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: July 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chao-I Wu
  • Patent number: 12015017
    Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: June 18, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai
  • Patent number: 11990428
    Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a die structure including a plurality of die regions and a plurality of first seal rings. Each of the plurality of first seal rings surrounds a corresponding die region of the plurality of die regions. The semiconductor device further includes a second seal ring surrounding the plurality of first seal rings and a plurality of connectors bonded to the die structure. Each of the plurality of connectors has an elongated plan-view shape. A long axis of the elongated plan-view shape of each of the plurality of connectors is oriented toward a center of the die structure.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hao Chun Liu, Ching-Wen Hsiao, Kuo-Ching Hsu, Mirng-Ji Lii
  • Patent number: 11991933
    Abstract: The present disclosure provides a magnetic random-access memory, comprising: an antiferromagnetic layer; a magnetic tunnel junction disposed on the antiferromagnetic layer and comprising a ferromagnetic layer disposed corresponding to the antiferromagnetic layer; wherein the ferromagnetic layer of the magnetic tunnel junction has in-plane magnetic anisotropy, and an exchange bias field is formed between the antiferromagnetic layer and the ferromagnetic layer by an annealing process. A direction of the exchange bias field is changed by a spin orbit torque, thereby changing a direction of a magnetic moment of the ferromagnetic layer and realizing data writing. The present disclosure can improve a thermal stability of the i-MTJ and reduce a lateral dimension of the i-MTJ, thereby improving a storage density of the magnetic memory.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: May 21, 2024
    Assignee: BEIHANG UNIVERSITY
    Inventors: Weisheng Zhao, Daoqian Zhu, Zongxia Guo, Kaihua Cao, Shouzhong Peng
  • Patent number: 11990563
    Abstract: A nanorod light emitting device, a method of manufacturing the same, and a display apparatus including the nanorod light emitting device are provided. The nanorod light emitting device includes a first semiconductor layer doped with a first conductivity type, a light emitting layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the light emitting layer and doped with a second conductivity type that is electrically opposite to the first conductivity type, wherein a distance between a lower surface of the first semiconductor layer and an upper surface of the second semiconductor layer is in a range of about 2 ?m to about 10 ?m, wherein a difference between a diameter of the upper surface of the second semiconductor layer and the lower surface of the first semiconductor layer is 10% or less of a diameter of the upper surface of the second semiconductor layer.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: May 21, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joohun Han, Junhee Choi, Nakhyun Kim, Dongho Kim, Jinjoo Park