Patents Examined by Hajar Kolahdouzan
  • Patent number: 12268106
    Abstract: A nonvolatile memory device includes a resistance switching layer, a gate on the resistance switching layer, a gate oxide layer between the resistance switching layer and the gate, and a source and a drain, spaced apart from each other, on the resistance switching layer. A resistance value of the resistance switching layer is changed based on an illumination of light irradiated onto the resistance switching layer and is maintained as a changed resistance value.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: April 1, 2025
    Assignees: Samsung Electronics Co., Ltd., President and Fellows Of Harvard College
    Inventors: Minhyun Lee, Houk Jang, Donhee Ham, Chengye Liu, Henry Hinton, Haeryong Kim, Hyeonjin Shin
  • Patent number: 12261195
    Abstract: The present disclosure provides a manufacturing method of a semiconductor structure, and a semiconductor structure. The manufacturing method of a semiconductor structure includes: forming a plurality of cylindrical capacitors in an initial structure; removing part of the initial structure to form trenches, the trenches expose partial sidewalls of the cylindrical capacitors and a substrate of the initial structure; forming a dielectric layer, the dielectric layer at least covers an exposed surface of each of the cylindrical capacitors; forming a first top electrode, the first top electrode covers a surface of the dielectric layer; and forming a second top electrode, the second top electrode covers a surface of the first top electrode. In an axial direction of each of the cylindrical capacitors, the second top electrode formed in each of the trenches has a discontinuous part, and an air gap is formed in the discontinuous part of the second top electrode.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: March 25, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Yulei Wu, Bin Yang
  • Patent number: 12262649
    Abstract: The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: March 25, 2025
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventor: Philippe Boivin
  • Patent number: 12249672
    Abstract: In an embodiment a method for manufacturing a semiconductor device include providing a growth substrate, depositing an n-doped first layer, depositing an active region on the n-doped first layer, depositing a second layer onto the active region, depositing magnesium (Mg) in the second layer and subsequently to depositing Mg, depositing zinc (Zn) in the second layer such that a concentration of Zn in the second layer decreases from a first value to a second value in a first area of the second layer adjacent to the active region, the first area being in a range of 5 nm to 200 nm.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: March 11, 2025
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Philipp Kreuter, Andreas Biebersdorf, Christoph Klemp, Jens Ebbecke, Ines Pietzonka, Petrus Sundgren
  • Patent number: 12224379
    Abstract: In an embodiment a method for producing optoelectronic semiconductor chips includes A) growing an AlInGaAsP semiconductor layer sequence on a growth substrate along a growth direction, wherein the semiconductor layer sequence includes an active zone for radiation generation, and wherein the active zone is composed of a plurality of alternating quantum well layers and barrier layers, B) generating a structured masking layer, C) regionally intermixing the quantum well layers and the barrier layers by applying an intermixing auxiliary through openings of the masking layer into the active zone in at least one intermixing region and D) singulating the semiconductor layer sequence into sub-regions for the semiconductor chips, wherein the barrier layers in A) are grown from [(AlxGa1-x)yIn1-y]zP1-z with x?0.5, and wherein the quantum well layers are grown in A) from [(AlaGa1-a)bIn1-b]cP1-c with o<a?0.2.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: February 11, 2025
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Felix Feix, Ines Pietzonka, Petrus Sundgren
  • Patent number: 12219885
    Abstract: A phase change memory includes a substrate, a plurality of first phase change elements on the substrate, a plurality of electrodes on the plurality of first phase change elements, and a second phase change element connecting the plurality of electrodes and disposed between the plurality of first phase change elements.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: February 4, 2025
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Zuoguang Liu, Arthur Gasasira
  • Patent number: 12207571
    Abstract: An interconnect structure includes: an interconnect layer containing a metal element as a main component and extending in a direction; a metal layer opposite to the interconnect layer, and a solid electrolyte layer between the interconnect layer and the metal layer. The solid electrolyte layer encloses the interconnect layer at least in a cross-sectional view taken along a plane orthogonal to the direction. The interconnect layer and the metal layer are electrically insulated from each other by the solid electrolyte layer.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: January 21, 2025
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Asami Nishikawa, Satoshi Shibata, Yu Nishitani, Tetsuya Asano, Takuji Tsujita, Yuta Sugimoto
  • Patent number: 12198996
    Abstract: An integrated fan-out package includes a first redistribution structure, a die, a plurality of conductive structures, an encapsulant, and a second redistribution structure. The die is bonded to the first redistribution structure through flip-chip bonding. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The second redistribution structure is disposed on the encapsulant and is electrically connected to the first redistribution structure through the conductive structures. The second redistribution structure includes at least one conductive pattern layer that is in physical contact with the encapsulant. Top surfaces of the conductive structures contacting the second redistribution structure are coplanar with a top surface of the encapsulant.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: January 14, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Hsien-Wen Liu, Shih-Ting Hung, Yi-Jou Lin, Tzu-Jui Fang, Po-Yao Chuang
  • Patent number: 12191399
    Abstract: A transistor with stable electrical characteristics. A semiconductor device includes a first insulator over a substrate, a second insulator over the first insulator, an oxide semiconductor in contact with at least part of a top surface of the second insulator, a third insulator in contact with at least part of a top surface of the oxide semiconductor, a first conductor and a second conductor electrically connected to the oxide semiconductor, a fourth insulator over the third insulator, a third conductor which is over the fourth insulator and at least part of which is between the first conductor and the second conductor, and a fifth insulator over the third conductor. The first insulator contains a halogen element.
    Type: Grant
    Filed: April 19, 2023
    Date of Patent: January 7, 2025
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Mitsuhiro Ichijo, Toshiya Endo, Akihisa Shimomura, Yuji Egi, Sachiaki Tezuka, Shunpei Yamazaki
  • Patent number: 12159956
    Abstract: Provided is an optoelectronic semiconductor chip including a semiconductor layer sequence having an active layer, a doped current spreading layer and an output coupling layer, which are arranged one above the other in this order. The active layer generates primary radiation during intended operation. The current spreading layer includes a larger lateral electrical conductivity than the output coupling layer. The output coupling layer includes output coupling structures for coupling out radiation on an exit side facing away from the active layer. The output coupling layer includes a lower absorption coefficient for primary radiation than the current spreading layer.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: December 3, 2024
    Assignee: OSRAM OLED GMBH
    Inventors: Sebastian Pickel, Katharina Werner, Bernd Böhm, Anna Strozecka-Assig, Anna Nirschl
  • Patent number: 12156488
    Abstract: A method includes providing a substrate having a main surface, forming a layer of thermally insulating material on the main surface, forming strips of phase change material on the layer of thermally insulating material such that strips of phase change material are separated from the main surface by thermally insulating material, forming first and second RF terminals on the main surface that are laterally spaced apart from one another and connected to the strips of phase change material, and forming a heater structure having heating elements that are configured to control a conductive connection between the first and second RF terminals by applying heat to the one or more strips of phase change material, wherein each of the strips of phase change material includes multiple outer faces, and wherein portions of both outer faces from the strips of phase change material are disposed against one of the heating elements.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: November 26, 2024
    Assignee: Infineon Technologies AG
    Inventors: Dominik Heiss, Martin Bartels, Christoph Glacer, Christoph Kadow, Matthias Markert, Hans Taddiken, Hans-Dieter Wohlmuth
  • Patent number: 12142647
    Abstract: A method of forming a semiconductor including forming a source/drain feature adjacent to a semiconductor layer stack disposed over a substrate. The method further includes forming a dummy fin adjacent to the source/drain feature and adjacent to the semiconductor layer stack. The method further includes performing an etching process from a backside of the substrate to remove a first portion of the dummy fin adjacent to the source/drain feature, thereby forming a first trench in the dummy fin, where the first trench extends from the dummy fin to the source/drain feature. The method further includes forming a first dielectric layer in the first trench and replacing a second portion of the dummy fin with a source/drain contact.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Han Fan, Wei-Yang Lee, Tzu-Hua Chiu, Chia-Pin Lin
  • Patent number: 12108604
    Abstract: Embodiments of the present disclosure provide an apparatus and methods for forming stair-like structures with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, an opening formed in the film stack, wherein the opening is filled with a channel layer and a center filling layer, and a protective liner layer disposed between the conductive structure and the channel layer.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: October 1, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Jaesoo Ahn, Thomas Kwon, Mahendra Pakala
  • Patent number: 12096705
    Abstract: A memory cell may include an active electrode, an inert electrode, and a dielectric positioned between them. A forward electrical bias between the electrodes may result in the formation of a conductive bridge between them. A reverse electrical bias may result in the dissolution of the conductive bridge. The memory cell may include nanotube structures formed within the dielectric, where the nanotube structures define columns between the active electrode and the inert electrode. A memory device may include multiple such conductive bridge memory cells. A method of forming a memory cell may include positioning an active electrode onto a substrate, positioning a dielectric layer onto the active electrode, forming nanotube structures within the dielectric layer while positioning the dielectric layer, where the nanotube structures define columns within the dielectric layer, and positioning an inert electrode onto the dielectric layer.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: September 17, 2024
    Assignee: Bosie State University
    Inventors: Maria Mitkova, Muhammad Rizwan Latif
  • Patent number: 12063873
    Abstract: A tunnel barrier layer includes a non-magnetic oxide, wherein a crystal structure of the tunnel barrier layer includes both an ordered spinel structure and a disordered spinel structure.
    Type: Grant
    Filed: January 13, 2023
    Date of Patent: August 13, 2024
    Assignee: TDK CORPORATION
    Inventors: Shinto Ichikawa, Katsuyuki Nakada
  • Patent number: 12062738
    Abstract: The invention described herein provides a method and apparatus to realize incorporation of Beryllium followed by activation to realize p-type materials of lower resistivity than is possible with Magnesium. Lower contact resistances and more effective electron confinement results from the higher hole concentrations made possible with this invention. The result is a higher efficiency GaN-based LED with higher current handling capability resulting in a brighter device of the same area.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: August 13, 2024
    Assignee: POWER INTEGRATIONS, INC.
    Inventors: James R. Shealy, Richard J. Brown
  • Patent number: 12057400
    Abstract: Some embodiments include an integrated assembly having a stack of alternating first and second levels. A panel extends through the stack. The first levels have proximal regions adjacent the panel, and have distal regions further from the panel than the proximal regions. The distal regions have first conductive structures, and the proximal regions have second conductive structures. Detectable interfaces are present where the first conductive structures join to the second conductive structures. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: August 6, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Shyam Surthi
  • Patent number: 12046625
    Abstract: Provided are a light-emitting element, a manufacturing method thereof, and a display device comprising the light-emitting element. The method for manufacturing the light-emitting element comprises the steps of: preparing a lower substrate including a substrate and a buffer material layer formed on the substrate, forming a separating layer disposed on the lower substrate and including at least one graphene layer, forming an element deposition structure by depositing a first conductivity type semiconductor layer, an active material layer, and a second conductivity type semiconductor layer on the separating layer, forming an element rod by etching the element deposition structure and the separating layer in a vertical direction; and separating the element rod from the lower substrate to form a light emitting element.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: July 23, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jung Hong Min, Dae Hyun Kim, Hyun Min Cho, Dong Uk Kim, Dong Eon Lee, Seung A Lee, Hyung Rae Cha
  • Patent number: 12046699
    Abstract: The invention described herein provides a method and apparatus to realize incorporation of Beryllium followed by activation to realize p-type materials of lower resistivity than is possible with Magnesium. Lower contact resistances and more effective electron confinement results from the higher hole concentrations made possible with this invention. The result is a higher efficiency GaN-based LED with higher current handling capability resulting in a brighter device of the same area.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: July 23, 2024
    Assignee: POWER INTEGRATIONS, INC.
    Inventors: James R. Shealy, Richard J. Brown
  • Patent number: 12048258
    Abstract: A phase change memory device includes a first electrode, a second electrode, a phase change region, a first spacer and a second spacer. The second electrode is disposed over the first electrode. The phase change region is disposed between the first and second electrodes. The first spacer laterally covers the phase change region. The second spacer laterally covers the first spacer, and has a thermal conductivity smaller than that of the first spacer.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Tai Tseng, Chang-Chih Huang, Kuo-Chyuan Tzeng