Abstract: A semiconductor device includes a gate stack with conductive layers and insulating layers that are stacked alternately with each other, a first channel pattern passing through the gate stack, a second channel pattern coupled to the first channel pattern, the second channel pattern protruding above a top surface of the gate stack, an insulating core formed in the first channel pattern, the insulating core extending into the second channel pattern, a gate liner with a first portion that surrounds a top surface of the gate stack and a second portion that surrounds a portion of a sidewall of the second channel pattern, and a barrier pattern coupled to the gate liner, the barrier pattern surrounding a remaining portion of the sidewall of the second channel pattern.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.

Abstract: A display device may include a first active layer disposed on a substrate, a scan line disposed on the first active layer, a lower gate signal line disposed on the scan line, an oxide semiconductor pattern disposed on the lower gate signal line, and including a channel part that overlaps the lower gate signal line and a low-resistance part formed on a side portion of the channel part, a metal pattern disposed on at least one surface of the low-resistance part, and an upper gate signal line disposed on the oxide semiconductor pattern to overlap the channel part.

Abstract: A display apparatus includes an upper substrate including a first area corresponding to a first light-emitting device; a second-color color filter layer on a lower surface of the upper substrate and including a first opening exposing the first area; a first-color color filter layer including a portion filling the first opening and a portion on a lower surface of the second-color color filter layer; a bank between the first-color and second-color color filter layers and a lower substrate, the bank including a second opening corresponding to the first area; and a first-color quantum dot layer filling the second opening, wherein the second opening includes a portion overlapping the first opening and a portion outside the first opening in a plan view.

Abstract: The present technology relates to a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a stack with a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked on a substrate, and a plurality of channel structures passing through the stack in a vertical direction. Each of the plurality of channel structures includes a core insulating layer, a channel layer, a tunnel insulating layer, and a charge storage layer that vertically extend in the same direction as the plurality of channel structures, and a dielectric constant of a partial region of the core insulating layer is lower than a dielectric constant of another region of the core insulating layer.

Abstract: The present application discloses an optical semiconductor device. The optical semiconductor device includes a logic die, a memory die, and a sensor die. The logic die includes a front surface. The memory die includes a front surface positioned on the front surface of the logic die, and a back surface opposite to the front surface of the memory die. The sensor die includes a front surface positioned on the back surface of the memory die, a back surface opposite to the front surface of the sensor die, a sensor unit located at the back surface of the sensor die, a color filter positioned on the back surface of the sensor die, and a micro-lens positioned on the color filter.