Abstract: According to an aspect of the present disclosure, a semiconductor device includes a substrate, a resin case surrounding a region just above the substrate in a planar view, a semiconductor chip provided in the region and an electrode including a first portion pulled out from an upper surface of the resin case and a second portion provided below the upper surface of the resin case and to be inserted into the resin case, and being electrically connected to the semiconductor chip, wherein a first notch is formed over the first portion to the second portion in the electrode, and a first groove is formed to expose a portion, formed in the second portion, in the first notch on the upper surface of the resin case.

Abstract: A semiconductor device according to an aspect of the present technology includes a low-concentration N-type region, a first high-concentration N-type region and a second high-concentration N-type region that are stacked with the low-concentration N-type region interposed therein, a gate electrode that surrounds the low-concentration N-type region as viewed from a stacking direction, which is a direction in which the low-concentration N-type region, the first high-concentration N-type region, and the second high-concentration N-type region are stacked, a first insulating film placed between the gate electrode and the low-concentration N-type region, and a second insulating film placed between the gate electrode and the first high-concentration N-type region. The first high-concentration N-type region is connected to one of a source electrode and a drain electrode. The second high-concentration N-type region is connected to the other of the source electrode and the drain electrode.

Abstract: An interposer for a curved detector. In some embodiments a system includes a curved array photodetector; a first readout integrated circuit, the first readout integrated circuit being substantially flat; and an interposer, between the photodetector and the first readout integrated circuit. The photodetector and the first readout integrated circuit may each have a plurality of electrical contacts. The interposer may include a first conductor connecting a first contact, of the plurality of electrical contacts of the photodetector, and a second contact, of the plurality of electrical contacts of the first readout integrated circuit.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.

Abstract: A semiconductor device may include a conductive layer over a semiconductor body and a first stress compensation layer adjacent to the conductive layer. The stress compensation layer may include a defined first stress.

Abstract: A light emitting element includes a light emitting portion, an intermediate layer covering the light emitting portion, an optical path control unit disposed on or above the intermediate layer, and a coating layer covering at least the optical path control unit. Light emitted from the light emitting portion passes through the intermediate layer, and enters then exits from the optical path control unit. The coating layer includes first and second coating layer. The first coating layer covers a part of an outer surface of the optical path control unit on the intermediate layer side. The second coating layer covers the first coating layer and the rest of the outer surface of the optical path control unit. Values of refractive indices of materials constituting the optical path control unit, the first coating layer, and the second coating layer are different from each other.

Abstract: A nano-FET and a method of forming is provided. In some embodiments, a nano-FET includes an epitaxial source/drain region contacting ends of a first nanostructure and a second nanostructure. The epitaxial source/drain region may include a first semiconductor material layer of a first semiconductor material, such that the first semiconductor material layer includes a first segment contacting the first nanostructure and a second segment contacting the second nanostructure, wherein the first segment is separated from the second segment. A second semiconductor material layer is formed over the first segment and the second segment. The second semiconductor material layer may include a second semiconductor material having a higher concentration of dopants of a first conductivity type than the first semiconductor material layer. The second semiconductor material layer may have a lower concentration percentage of silicon than the first semiconductor material layer.

Abstract: Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.

Abstract: A quantum dot including a core including a first semiconductor nanocrystal including zinc, selenium, and tellurium, and a semiconductor nanocrystal shell disposed on the core, the semiconductor nanocrystal shell including zinc, and selenium, sulfur, or a combination thereof, wherein the quantum dot does not include cadmium, a mole ratio of tellurium relative to selenium in the first semiconductor nanocrystal is greater than about 1:1, a mole ratio of a sum of selenium and sulfur relative to in the quantum dot is greater than about 1:1, a wavelength of a maximum emission peak of the quantum dot is in a range of about 500 nanometers (nm) to about 550 nm, and the quantum dot has quantum efficiency (QY) of greater than or equal to about 30%, a quantum dot-polymer composite including the quantum dot, a display device including the quantum dot-polymer composite, and an electroluminescent device including the quantum dot.

Abstract: A semiconductor device, comprises a source, and a drain spaced apart from the source in a first direction. A channel layer is disposed on radially outer surfaces of the source and the drain in a second direction orthogonal to the first direction. A memory layer is disposed on a radially outer surface of the channel layer. A via is disposed at an axial end of the drain and is configured to electrically couple the drain to a global drain line. The via comprises a via base extending in a plane defined by the first direction and a second direction perpendicular to the first direction, and structured to contact the corresponding global drain line, and via sidewalls extending from outer peripheral edges of the base towards the drain. The via defines an internal cavity within which at least a portion of the axial end of the drain is disposed.

Abstract: Embodiments of the invention include a semiconductor device having a fin-shaped channel with a bottom surface, sidewalls and a top surface. A first source or drain (S/D) region is communicatively coupled to the fin-shaped channel, and a sub-channel region is between the bottom surface of the fin-shaped channel and a substrate. A U-shaped dielectric region within a first portion of the sub-channel region, wherein the U-shaped dielectric region includes a bottom isolation layer and a first inner spacer region. A wrap-around gate structure extends around the bottom surface, the sidewalls and the top surface of the fin-shaped channel, wherein a bottom region of the wrap-around gate structure is within a second portion of the sub-channel region.

Abstract: In some embodiments, a method includes forming a plurality of nanostructures over a substrate; etching the plurality of nanostructures to form first recesses; forming source/drain regions in the first recesses; removing first nanostructures of the plurality of nanostructures leaving second nanostructures of the plurality of nanostructures; depositing a gate dielectric over and around the second nanostructures; performing an aluminum treatment on the gate dielectric; depositing a first conductive material over and around the gate dielectric; performing a fluorine treatment on the first conductive material; and depositing a second conductive material over and around the first conductive material.

Abstract: A 3D memory device includes a memory stack and a support structure. The memory stack, on a substrate, includes a core region and a non-core region neighboring the core region. The support structure extends in the non-core region and into the substrate. The support structure includes a first support portion and a second support portion over the first support portion. The first support portion has a stiffness higher than the second support portion.

Abstract: A display panel includes a base substrate including a first display region and a second display region disposed on a side of the first display region. The display panel also includes a first anode layer, a first light-emitting layer and a first cathode layer which are disposed in the first display region and are sequentially laminated in a direction distal from the base substrate. The display panel also includes a second anode layer, a second light-emitting layer and a second cathode layer which are disposed in the second display region and are sequentially laminated in a direction distal from the base substrate.

Abstract: A display panel includes: a first base substrate and a second base substrate which are opposite to each other, and a plurality of lens imaging modules. The first base substrate includes a plurality of pixel units arranged in an array. The plurality of lens imaging modules are located between the first base substrate and the second base substrate, and an orthogonal projection of the lens imaging module on the first base substrate is located between two adjacent pixel units. Therefore, the lens imaging modules are disposed inside the display panel without affecting display of the display panel, such that a screen-to-body ratio can be significantly increased, which is advantageous for achieving borderless full-screen display.

Abstract: A display device includes pixels including subpixels, electrodes spaced apart from each other in a first direction, extending in a second direction, and disposed in the subpixels, light emitting elements in the subpixels and on the electrodes, and contact electrodes electrically contacting the light emitting elements and the electrodes. The subpixels each includes an emission area including the light emitting elements, and a sub area spaced apart from the emission area. The pixels each includes a first subpixel including a first emission area and a sub area on a first side of the first emission area, and a second subpixel which is disposed on a first side of the first subpixel and includes a second emission area and a sub area disposed on a second side of the second emission area. The sub area of the second subpixel is disposed side by side with the first emission area.

Abstract: A semiconductor device includes a gate stack with conductive layers and insulating layers that are stacked alternately with each other, a first channel pattern passing through the gate stack, a second channel pattern coupled to the first channel pattern, the second channel pattern protruding above a top surface of the gate stack, an insulating core formed in the first channel pattern, the insulating core extending into the second channel pattern, a gate liner with a first portion that surrounds a top surface of the gate stack and a second portion that surrounds a portion of a sidewall of the second channel pattern, and a barrier pattern coupled to the gate liner, the barrier pattern surrounding a remaining portion of the sidewall of the second channel pattern.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.

Abstract: A display device may include a first active layer disposed on a substrate, a scan line disposed on the first active layer, a lower gate signal line disposed on the scan line, an oxide semiconductor pattern disposed on the lower gate signal line, and including a channel part that overlaps the lower gate signal line and a low-resistance part formed on a side portion of the channel part, a metal pattern disposed on at least one surface of the low-resistance part, and an upper gate signal line disposed on the oxide semiconductor pattern to overlap the channel part.

Abstract: A display apparatus includes an upper substrate including a first area corresponding to a first light-emitting device; a second-color color filter layer on a lower surface of the upper substrate and including a first opening exposing the first area; a first-color color filter layer including a portion filling the first opening and a portion on a lower surface of the second-color color filter layer; a bank between the first-color and second-color color filter layers and a lower substrate, the bank including a second opening corresponding to the first area; and a first-color quantum dot layer filling the second opening, wherein the second opening includes a portion overlapping the first opening and a portion outside the first opening in a plan view.