Abstract: A method includes storing a plurality of data RAM, holding information for all outstanding requests forwarded to a next-level memory subsystem, clearing information associated with a serviced request after the request has been fulfilled, determining if a subsequent request matches an address supplied to one or more requests already in-flight to the next-level memory subsystem, matching fulfilled requests serviced by the next-level memory subsystem to at least one requester who issued requests while an original request was in-flight to the next level memory subsystem, storing information specific to each request comprising a set attribute and a way attribute configured to identify where the returned data should be held in the data RAM once the data is returned, the information specific to each request further including at least one of thread ID, instruction queue position and color, and scheduling hit and miss data returns.

Abstract: The present solution provides a multi-tiered caching and cache indexing system is depicted. A cache management system uses a memory based object index to reference or identify corresponding objects stored in disk. The memory used to index object may grow proportionally or in relation to growth in the size of the disk. The techniques described herein minimize, reduce or maintain the size of memory for an object index although the size of storage for storing objects is changed. These techniques allow for more optimal use of memory for object indexing while increasing or decreasing disk size for object storage.

Abstract: A scalable reconfigurable register file (SRRF) containing multiple register files, read and write multiplexer complexes, and a control unit operating in response to instructions is described. Multiple address configurations of the register files are supported by each instruction and different configurations are operable simultaneously during a single instruction execution. For example, with separate files of the size 32×32 supported configurations of 128×32 bit s, 64×64 bit s and 32×128 bit s can be in operation each cycle. Single width, double width, quad width operands are optimally supported without increasing the register file size and without increasing the number of register file read or write ports.

Abstract: Methods and systems provide recognition of a device in a daisy chain cascade configuration. Input circuitry at a device receives an input signal that indicates device configuration following a power-up, reset or other operation of the device. A pulse generator generates a pulse in response to the operation, the pulse occurring while the input signal indicates device configuration. A state latch register stores the state of the input signal in response to the received pulse, thereby storing a state indicating configuration of the respective device. Following this operation, the input circuitry may receive signals unrelated to the device configuration, thereby obviating the need for additional pin assignment.

Abstract: A design structure embodied in a machine readable storage medium for of designing, manufacturing, and/or testing for shared cache eviction in a multi-core processing environment having a cache shared by a plurality of processor cores is provided. The design structure includes means for receiving from a processor core a request to load a cache line in the shared cache; means for determining whether the shared cache is full; means for determining whether a cache line is stored in the shared cache that has been accessed by fewer than all the processor cores sharing the cache if the shared cache is full; and means for evicting a cache line that has been accessed by fewer than all the processor cores sharing the cache if a cache line is stored in the shared cache that has been accessed by fewer than all the processor cores sharing the cache.

Abstract: A cache memory control circuit includes a selecting section configured to be capable of selecting, in a predetermined order, each way or a predetermined two or more ways of a cache memory having multiple ways; a comparing section configured to detect a cache hit in each way; and a control section configured to, upon detection of a cache hit, stop a selection of the respective ways or the predetermined two or more ways at the selecting section.

Abstract: Techniques for allocating/reducing storage required for one or more virtual machines are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for allocating storage for one or more virtual machines. The method may comprise providing one or more virtual machines. The method may also comprise creating one or more master images containing one or more commonly used blocks. The method may also comprise creating one or more Copy on Write volumes, where each Copy on Write volume may be associated with at least one of the one or more virtual machines and at least one of the one or more master images, and wherein updated blocks may be stored in at least one of the one or more Copy on Write volumes, thereby reducing storage required for one or more virtual machines.

Abstract: A flash memory includes a data area in which first and second k-bit data (k is a natural number) are stored; and an additional data area in which a first additional m-bit data (m is a natural number) and a second additional m-bit data used to respectively identify the first and second data are stored. The first additional data and the second additional data have different values.

Abstract: A memory device comprises a memory array, a status register coupled with the memory array, and a security register coupled with the memory array and the status register. The memory array contains a number of memory blocks configured to have independent access control. The status register includes at least one protection bit indicative of a write-protection status of at least one corresponding block of the memory blocks that corresponds to the protection bit. The security register includes at least one register-protection bit. The register-protection bit is programmable to a memory-protection state for preventing a state change of at least the protection bit of the status register. The register-protection bit is configured to remain in the memory-protection state until the resetting of the memory device.

Abstract: A digital data reproducing apparatus comprising: a reading unit configured to read digital data stored in a recording medium at a speed higher than a reproduction speed to store the digital data into a first memory; an encoding unit configured to store encoded data obtained by encoding the digital data read by the reading unit into a second memory; a reproducing unit configured to reproduce the digital data stored in the first memory at the reproduction speed; and a transferring unit configured to transfer the encoded data stored in the second memory into a third memory different from the second memory.

Abstract: A processing system and method is disclosed wherein a processor may be configured to predict an address of memory from which data will be needed, transmit to a memory controller a pre-fetch command for the data at the predicted address of the memory, and transmit to the memory controller a read request for the data at the predicted address of the memory if the data is needed.

Abstract: A flash memory-based storage grouped into memory regions is controlled by determining whether the flash memory is accessed or not. Power to a first of the memory regions is controlled according to the determination result. Power to a second of the memory regions is controlled according to the determination result. Controlling includes enabling provision of power to the first memory region while concurrently denying power to the second memory region.

Abstract: Methods for a treatment of cached objects are described. In one embodiment, management of a region of a cache is configured with an eviction policy plug-in and a storage plug-in. The eviction policy plug-in includes code to evict an object that is cached in the region of cache. The storage plug-in includes code to execute a function involving a key attribute manipulation function that, using a first hashing function and a key, identifies a table of attributes for the first object located within the region of cache, and using a second hashing function and an attribute name, gets a specific attribute for the first object from the table, the key being registered with the storage plug-in.

Abstract: A system for minimizing downtime in an appliance-based business continuance architecture is provided. The system includes at least one primary data storage and least one primary host machine. The system includes an intercept agent to intercept primary host machine data requests, and to collect information associated with the intercepted data requests. Moreover, at least one business continuance appliance in communication with the primary host machine and in communication with a remote backup site is provided. The appliance receives information associated with the intercepted data requests from the intercept agent. In addition, a local cache is included within the business continuance appliance. The local cache maintains copies of primary data storage according to the information received. Furthermore, the remote site is provided with the intercepted data requests via the business continuance appliance, wherein the remote site maintains a backup of the primary data storage.

Abstract: A disk array device enabling an appropriate estimation of a physical disk capacity necessary prior to introducing a snapshot function. If a valid flag of the snapshot simulation function of a specified logical volume is on at receiving a data updating request from the host 100, snapshot simulation function control means 21 inquiries with update range determination means 10 and receives notice of bits on a bitmap corresponding to a range of update data, sets corresponding bits on a bitmap of the specified logical volume of bitmap information storage means 12 by means of bitmap information updating means 11, and executes data updating processing. Upon receiving an instruction of reporting a simulation result, snapshot simulation result reporting means 22 reports a physical disk capacity of the snapshot calculated by the snapshot simulation function.

Abstract: A method and apparatus for overwriting data in a recording medium, such as a Blu-ray disc write-once (BD-WO), are disclosed. The method includes when receiving a plurality of data record commands for a previously recorded area within the recording medium, replacement recording the received data for each record command on a non-recorded area within the recording medium, and when the plurality of record commands occur in a continuous area within the recording medium, the data is recorded on a management area within the recording medium as a management information for the plurality of record commands.

Abstract: A multiple-core processor providing a flexible cache directory scheme. In one embodiment, a processor may include a second-level cache including a number of cache banks and a respective number of cache directories corresponding to the cache banks. The processor may further include a number of processor cores configured to access the cache banks, as well as core/bank mapping logic coupled to the second-level cache and the processor cores. Each of the processor cores may include a respective first-level cache. Each of the respective cache directories may be configured to store directory state information associated with portions of respective first-level caches of at least two of the processor cores. If fewer than all of the cache banks are enabled, the core/bank mapping logic may be configured to completely map directory state information associated with each respective first-level cache of enabled processor cores to respective cache directories associated with enabled cache banks.

Abstract: The present invention provides a controller that can write an operation program for a control circuit to a memory and a method for writing data, while suppressing an increase in circuit area and an increase in manufacturing cost. An ATA register is connected to a host computer. An ATAPI register is connected to the ATA register. When a command code A0h is sent to the ATA register from the host computer, data (a command and microcomputer control software) sent from the host computer is sent to the ATAPI register via the ATA register. A decoder decodes the data sent to the ATAPI register and generates an address and data for writing the microcomputer control software to the flash ROM.

Abstract: An electronic apparatus includes first and second processors which execute first and second operating systems, first disk controller which accesses a disk storage device in response to a disk access request from the first processor, a second disk controller which accesses the disk storage device in response to a disk access request from the second processor, a switch device to connect one of the first and second disk controllers to the disk storage device, and a unit for switching an access path, which is used when the first processor accesses the disk storage device, between a first access pass in which the first processor executes access to the disk storage device via the second processor, and a second access pass in which the first processor executes access to the disk storage device without intervention of the second processor.

Abstract: A memory card device includes a host interface unit configured to receive a plurality of commands from a host apparatus, the commands including at least a memory access command with a memory address of a specific bit width, a nonvolatile semiconductor memory which includes a storage area whose memory size is larger than a maximum memory size that is addressable by the memory address, a bank identification number management unit configured to divide the storage area into a plurality of banks and manage a plurality of bank identification numbers corresponding to the banks, a bank designation unit configured to designate one of the banks in accordance with a bank identification number included in a bank designation command transmitted from the host apparatus, and a memory control unit configured to access the designated one of the banks in accordance with the memory access command with the memory address.