Abstract: Virtual data storage cartridges are created on a data storage subsystem to/from which volume writes and reads are directed. When a number of data volumes have been written, the controller may migrate them to the tape drive, a much faster process than writing directly to tape and enabling multiple logical volumes to be written to a single physical tape. With the present invention, virtual scratch cartridges are virtually premounted in a virtual drive loader while the virtual drive is accessing another virtual cartridge. When the host calls for a new scratch cartridge, it can be mounted in the virtual drive almost immediately, having already been virtually pre-loaded.

Abstract: A method and apparatus for simulating the design of an integrated circuit uses a processor (200). The processor (200) executes a simulator (540) from memory (280) to exercise a model (544). The data points (15-27) of an output signal are stored in a history data file (542). The techniques used to generate each of the data points (15-27) are also stored in the history data in file (542). The history data are then used to generate a converted output signal that has a uniform time scale. If the converted output signal requires the generation of a desired data point, then the approximation technique used to generate the following data point stored in the history data (542) is used.

Abstract: A system and method for detecting architectural violations of strongly ordered instructions by a computer architecture under test that supports out-of-order instruction execution is presented. A synchronizer concurrently controls the execution of an architectural model, which models high-level architectural requirements of the computer architecture under test and generates correct results under all received instruction test stimuli, and a behavioral model, which models the high-level architectural requirements of the computer architecture under test and executes instruction test stimuli according to the out-f-order instruction execution behavior defined by the computer architecture. The synchronizer matches all out-of-order instruction execution effects.

Abstract: An apparatus and method for directing a computer system to transform a plurality of data in a planning data structure into a scheduling data structure. Each entry of the scheduling data structure has at least a start date, quantity, and duration.

Abstract: Method for providing slave direct memory access (DMA) support on a computer system bus that does not support slave devices, such as the personal computer interconnect or "PCI" bus. Using the method, an adapter card or microprocessor with a local DMA controller can be operated as a busmaster and simulate a system DMA controller which would normally be used during slave DMA operations. Alternatively, the method allows a local DMA controller to work with an existing system DMA controller so that application software receives the correct status when polling registers in the system DMA controller. The method allows the system DMA controller to operate as if the system DMA controller is controlling DMA transfers. In this way device contention between the system DMA controller and the local DMA controller is avoided.