Abstract: The present disclosure provides a dynamic random access memory (DRAM). The DRAM includes a plurality of banks, a power source and a control device. Each of the banks includes a plurality of subarrays. The control device derives information on a quantity of operated subarrays among the subarrays, and determines how much electrical energy to provide based on the information. The power source provides the resultant amount of electrical energy based on the determination from the control device.

Abstract: A system, a memory device and a method are contemplated in which the apparatus may include a plurality of memory cells, a plurality of voltage reduction circuits, and control circuitry. The plurality of voltage reduction circuits may be configured to reduce a voltage level of a power supply coupled to the plurality of memory cells. The control circuitry may be configured to select one of the voltage reduction circuits based on one or more operating parameters. The control circuitry may be further configured to activate the selected voltage reduction circuit upon receiving a write command directed towards the memory cells. The control circuitry may be further configured to execute the write command. Upon completion of the write command, the control circuitry may be further configured to de-activate the selected one of the voltage reduction circuits.

Abstract: A data storage device includes a memory and a controller and may perform a method that includes updating, in the controller, a value of a particular counter of a set of counters in response to an erase operation to a particular region of the non-volatile memory that is tracked by the particular counter. The method includes, in response to the value of the particular counter indicating that a count of erase operations to the particular region satisfies a first threshold, initiating a remedial action to the particular region of the non-volatile memory.

Abstract: According to one embodiment, in a nonvolatile semiconductor memory device, a data latch circuit which is connected to a sense amplifier circuit controls a data writing operation and a data reading operation to and from a nonvolatile memory cell array through a data bus, and outputs the stored data to the data bus when the sense amplifier circuit performs the data writing operation. The data latch circuit is provided with two nodes respectively storing and outputting normal data and reverse data which are connected to the data bus.

Abstract: When data erasure of a flash memory is interrupted and restarted from the interrupted point, time required for the data erasure is shortened. A flash memory includes a memory cell(s), a verification circuit, and a power supply circuit. The verification circuit measures a threshold voltage of the memory cell(s) by verifying an erasure state of the memory cell(s). The power supply circuit applies, to the memory cell(s), one or more pulse voltages whose initial pulse voltage has a strength that corresponds to the measured threshold voltage.

Abstract: To reduce current consumption, there is provided a circuit for each bank, comprising selection circuits 26 through 28 each for selecting either a normal supply voltage Vii or a higher supply voltage Vjj as a supply voltage VH0 in response to a selection control signals SC0 and *SC0, a selection control circuit 22 for generating the signals SC0 and *SC0 to make the selection circuits select Vii when a bank activation signal BRAS0 is inactive and Vjj for a predetermined period in response to activation of BRAS0, and sense amplifier driving circuits 111 through 113 for supplying the ground voltage and VH0 to the sense amplifier rows in response to activation of sense amplifier control signals. To stabilize the output voltage Vii of the power supply circuit having a NMOS transistor, the drain electrode, gate and source electrodes of which are at VCC, VG and approximately Vii=VG-Vth, where Vth is the threshold voltage of the NMOS transistor 45, a leak circuit is employed.

Abstract: A static, low-power differential sense amplifier (DSA) and method includes operation of cross-linked channels having complementary differential nodes separated from ground by corresponding parallel-transistor pairs. The DSA output channels have complementary output nodes separated from ground by corresponding parallel-transistor pairs. The DSA further includes logic gates to produce a sense amplifier output. Each logic gate is driven by a corresponding complementary differential node and an opposite complimentary output node. The DSA includes transistors activating a done line under control of the complementary differential nodes.

Abstract: One memory array is divided into a plurality of banks sharing a row of memory cells. Global IO buses are disposed for memory column blocks forming the plurality of banks included in one memory array. The global IO buses are selectively and electrically connected to the same data input/output terminal.