Abstract: For using a plurality of files contained in one logical device with a plurality of processing systems, sharing of a data storage unit among the plurality of processing systems is realized without need for a host processing system to check use states of the files in a server storage unit. Information concerning extent (extent range) of an input/output processing request issued by a host processor is stored in a control memory incorporated in a control unit for allowing the control unit to make decision as to overlap of the extents of the input/output processings to thereby effectuate exclusive control on an extent-by-extent basis.

Abstract: A data processing apparatus and method of handling write transactions in such an apparatus is provided. The apparatus has a plurality of devices, and bus circuitry providing connection paths between the plurality of devices. At least one of the devices has a bus master interface operable to generate write transactions for output via the bus circuitry, whilst at least one of the devices has a bus slave interface operable to receive the write transactions from the bus circuitry. A write transaction includes transferring a write address from a bus master interface to a bus slave interface and separately transferring write data from the bus master interface to the bus slave interface. In accordance with embodiments of the present invention, the bus master interface is allowed to generate a write transaction such that the write data is received at the bus slave interface before the associated write address. This leads to a significant decrease in the complexity of the apparatus.

Abstract: A protocol adapter for transferring diagnostic messages between networks within a vehicle and a host computer. The protocol adapter operates as a voltage translator to support J1708 software. The protocol adapter also recognizes when the protocol adapter is connected to a host computer running the J1939 and/or J1708 protocols and automatically switches to that protocol.

Abstract: For using a plurality of files contained in one logical device with a plurality of processing systems, sharing of a data storage unit among the plurality of processing systems is realized without need for a host processing system to check use states of the files in a server storage unit. Information concerning extent (extent range) of an input/output processing request issued by a host processor is stored in a control memory incorporated in a control unit for allowing the control unit to make decision as to overlap of the extents of the input/output processings to thereby effectuate exclusive control on an extent-by-extent basis.

Abstract: A system for providing a command stream that includes a controller chip is disclosed. The controller chip includes an engine operative to manage a memory. The engine includes an interface. A storage element is coupled to the engine and the storage element is accessible by a central processing unit (CPU) through the engine. The engine receives commands from the CPU via the interface, manages the storage element via the interface and writes the commands into the memory. The engine incorporates the storage element as part of the memory.

Abstract: A performance counter accumulates a value by periodically adding a variable increment value representing the amount of work performed. The increment value can be varied in dependence upon the processor clock frequency and may be adjusted under hardware and/or software control.

Abstract: A command accumulation tool, a testing tool for a queue, and a method, are provided, which, for example, may cause commands to accumulate in queue(s). In one embodiment, a testing tool comprises an I/O interface for connecting with a target having the queue(s); and an I/O interface for connecting with initiator(s). Trigger logic intercepts a predetermined response at the target I/O interface from a target to an initiator with respect to a command of the initiator, and asserts a trigger signal. Outbound logic responds to the trigger signal, providing a reject and retry response at the target I/O interface for the target with respect to the response from the target, whereby a timeout timer for the command of the initiator is stopped for the queue(s). The outbound logic additionally conducts flow control with respect to the target at the target I/O interface.

Abstract: A hardware component is monitored in a computing system. The utilization of the hardware component is sampled at a predefined sampling rate for a predefined sampling period. The proportion of the sampled values taken during the sampling period that fall within a predefined range of values is determined. A value representative of the proportion along with time information identifying the time of the sampling period is stored. Storing occurs when the value representative of the proportion exceeds a predefined threshold.

Abstract: A scanner system includes a scanner, computers sharing the scanner, a network connecting between them, and a scanner controlling apparatus connected between the network and the scanner. The computer includes a device driver to control the scanner and notify the scanner controlling apparatus of an event in the device driver, and an application to control the device driver, and transmit and receive data to and from the scanner controlling apparatus. The application activates the device driver in response to the trigger input from the scanner controlling apparatus. When activating, the device driver receives image data from the scanner controlling apparatus through the application.

Abstract: Techniques for verifying input/output (I/O) command data are provided. Information about the contents of the data are specified in the I/O command. After an application issues the I/O command, a subsequent component, such as a controller, uses the information to verify the contents of the data before the I/O command is performed.

Abstract: An information provision method for providing information to deal with an abnormality occurred in a peripheral device, comprising: notifying the abnormality to a host apparatus which controls the peripheral device, obtaining a storage location for information corresponding to the abnormality occurred in the peripheral device from a database which holds the storage location for information corresponding to the abnormality, obtaining information located in the storage location from a server, and displaying the information obtained from the server on a display terminal of the host apparatus.

Abstract: A CANOpen network including a bus master and an I/O module is disclosed. Each is communicatively coupled to a common bus. The I/O module is subject to a state change. The bus master collects state information from the I/O module by determining if the bus master is prepared to receive further data from the bus and sending a trigger signal from the bus master to the I/O module if the bus master is prepared to receive further data from the bus. The I/O modules sends a state signal to the bus master in response to the trigger signal.

Abstract: Disclosed is a disk control apparatus with excellent scalability realized on the same architecture, in high quality and reliability, regardless of its scale. Each of a plurality of channel interface units and a cache memory unit as well as each of a plurality of disk interface units and the cache memory unit are connected through a switch and a data path network (solid line) in each disk control cluster. Each switch provided outside each disk control cluster is connected to the switch in each disk control cluster through the data path network. A resource management unit is provided outside each disk control cluster and the resource management unit is connected to each of the plurality of channel interface units/disk interface units, as well as to the cache memory unit in each disk control cluster. The resource management unit is also connected to each switch provided outside each disk control cluster through a resource management network (dotted line).

Abstract: An arrangement is provided for ingress processing optimization via traffic classification and grouping. A plurality of packets are classified according to a classification criterion. The classified packets are used to generate a packet bundle containing packets that are uniform with respect to the classification criterion. The packet bundle and its corresponding packet bundle descriptor are transferred to a host which then processes the packet bundle as a whole according to the information contained in the packet bundle descriptor.

Abstract: A method of asynchronously transferring data from a low speed bus to a high speed bus, comprises latching data at a first predetermined instant in a cycle of the clock frequency of the high speed bus, latching data at a second predetermined instant in the same cycle of the clock frequency of the high speed bus, a time period between the second and first predetermined instants being less than the period of the data, and either, if the values of the latched data at the first and second predetermined instants are equal, the latched data is transferred at a third predetermined instant onto the high speed bus, or, if the values sampled at the first and second predetermined instants are different, at the third predetermined instant, transferring the value of the currently present data is transferred onto the high speed bus.

Abstract: A physical layer apparatus compliant for both serial and parallel ATA interfaces is devised. The physical layer apparatus includes a serial ATA physical layer circuit, a channel selection unit and a channel selection controller. The channel selection unit is connected to a media access controller of a host through a first IDE bus. The channel selection unit is further selectively connected to a serial ATA device through the serial ATA physical circuit or connected to a parallel ATA device through second IDE bus. Therefore, the media access controller of the host can selectively access the serial ATA device and the parallel ATA device through the channel selection unit under the control of the channel selection controller.

Abstract: A DMA (Direct Memory Access) Exchange Block (DXB) processor may include a receive processor for writing data from a local memory to a host memory over a bus, e.g., a Peripheral Component Interconnect Extended (PCI/X) bus, and a transmit processor for writing data retrieved from the host memory over the bus to the local memory. Each processor may include a high priority queue and a normal priority queue. A controlling program generates DXBs, each of which include a tag assigned by the controlling program and memory descriptors corresponding to a direct memory access operation. The memory descriptor may include a host memory descriptor (address/length) and one or more local memory descriptors. The controlling program writes a DXB to one of the queues in a cache line spill operation. The transfer processor may include two channel registers, enabling the processor to perform two PCI/X data transfers simultaneously.

Abstract: A scheduling method and apparatus for use by a processor that controls storage devices of a data storage system is presented. The method allocates processing time between I/O operations and background operations for predetermined time slots based on an indicator of processor workload.

Abstract: A network connection state can be conveniently changed to a wired or a wireless connection state according to whether a portable computer body is attached to a docking station including an Access Point part or not.

Abstract: A wearable computer system includes a processing unit (102) and a number of peripherals. The processing unit and peripherals are coupled in a daisy-chain fashion utilizing a serial bus (120). The processing unit has a single connector for implementing the serial bus, and peripherals each have two connectors for propagating the serial bus. The wearable computer system has only one unused connector at any one time, thereby reducing excess bulk and weight due to excessive unused connectors. When a peripheral interrupts the processing unit, the processing unit relinquishes the serial bus to the interrupting peripheral. Alternatively, peripherals are assigned time slots within which the peripherals can utilize the serial bus.