Patents Examined by Harold T. Pitts
  • Patent number: 4833306
    Abstract: A remote recognition system for monitoring the progress of a plurality of batches of semiconductor wafers or memory disks through a series of processing operations based on bar code recognition technology. Each batch is placed in a carrier in which it is transported to various locations where processing operations are performed. Each carrier is provided with an optically visible bar code tag, coded to be responsive to within reading range of a bar code reader unit which transmits a modulated light beam signal to the coded bar code tag and reads and decodes the light beam reflected back and collected by an optical receiver to uniquely identify the carrier that is positioned within range of the reader unit. Information from the reader units to permit monitoring the progress of semiconductor wafer or memory disk batches through multiple processing operations is received by further control apparatus.
    Type: Grant
    Filed: May 18, 1988
    Date of Patent: May 23, 1989
    Assignee: Fluoroware, Inc.
    Inventor: Lynn Milbrett
  • Patent number: 4246539
    Abstract: A frequency synthesizing system for use in an AM.multidot.SSB transceiver of double conversion type comprising a single crystal oscillator in its PLL synthesizer. The fundamental frequency of the PLL synthesizer provided by the oscillation of the crystal oscillator is selected to be n times (where n is an even number) the second intermediate frequency of the transceiver so that all the frequencies required for the operation of the AM.multidot.SSB transceiver can be derived from the oscillation frequency of the single crystal oscillator, whereby to simplify the structure of the AM.multidot.SSB transceiver and to facilitate the adjustment of the transceiver.
    Type: Grant
    Filed: April 16, 1979
    Date of Patent: January 20, 1981
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroshi Haruki, Masahiro Watanabe
  • Patent number: 4081792
    Abstract: A monolithically integrated semiconductor matrix circuit arrangement comprising switching elements which are connected in pairs at one terminal. This common terminal of the pair of switching elements is connected to an input (or output) circuit path and other terminal of each switching element is connected individually to an output (or input) circuit path respectively.
    Type: Grant
    Filed: March 26, 1976
    Date of Patent: March 28, 1978
    Assignee: Licentia Patent-Verwaltungs-G.m.b.H.
    Inventors: Hans Schussler, Hans-Jurgen Wulf, Bernhard Rall, Helmut Knapp