Abstract: A pulse generating circuit is coupled to an address decoder to provide the address enable signal to the address decoder. An input pulse is provided to the pulse generating circuit and the output of the pulse generating circuit is coupled to the address decoder. The output of the pulse generating circuit keeps the address decoder enabled until the trailing edge of the input pulse. Internal to the pulse generating circuit the input pulse is connected to a delay. The output of the delay is connected to a first NOR gate. Another input of the first NOR gate receives the input pulse. The output of the first NOR gate is connected to a second NOR gate. Another input of the second NOR gate also receives the input pulse. The output of the second NOR gate is the output of the pulse generating circuit which is coupled to the address decoder. The pulse generating circuit provides a momentary output pulse at the trailing edge of the input pulse to momentarily inhibit the address decoder.