Abstract: A method and apparatus for optimizing data compression in a wireless digital access system (606) is described. The capability to establish a data compression session (216) spanning two communication links (604 and 605) is provided. Common compression parameters compatible with both communication links (604 and 605) are coordinated. Unnecessary processing is avoided, thereby reducing the processing load of a control processor (204) used in conjunction with the invention.

Abstract: A system and method for maintaining timing in a CDMA rake receiver has a global chip counter that counts CDMA signal chips as they arrive at the CDMA rake receiver. A local pseudo-noise (PN) sequence replica of the incoming CDMA signal is generated and used to perform a sliding window correlation of the locally generated PN sequence replica with the incoming signal to correlate the CDMA signal timing relative to stored CDMA signal chip counts. The PN sequence timing is maintained relative to GCC, which avoids having to keep track of absolute time within each Rake finger.

Abstract: A method and a device are provided for acquiring synchronization to a received digital signal. The signal consists of consecutive frames with a frame synchronization pattern distributed over a significant part of a frame. A number of blocks of constant length (303) are received (302) and a passage is selected (304) from the same location within each received block. A regularly occurring bit value is observed (305, 306) at a constant bit position within the selected passages. As a response to an observed regularly occurring bit value, the corresponding position in the received digital signal is used (308, 309) as a starting point, and the rest of the distributed frame synchronization pattern is located within the received digital signal.

Abstract: Systems and methods for enabling data transfers over communications links having a plurality of transmission lanes. In one embodiment, a system comprises a plurality of elastic buffers, each of which is coupled to one of the lanes in the communications link, and a buffer controller coupled to the buffers. Data is clocked into the elastic buffers using a first clock signal and is clocked out of the buffers by a second clock signal. The buffer controller is configured to monitor each of the buffers and to detect impending underflow or overflow conditions. In response to detect in one of these conditions, the buffer controller will cause the words to be added or deleted, respectively, to all of the elastic buffers rather than only the buffer in which the overflow/underflow condition was detected.

Abstract: A digital filter includes a number of coefficient generators that are clocked by a clock having a frequency including an undesired component. The coefficient generators, which each have a number of states, are communicatively coupled to multipliers that receive incoming signals and multiply the incoming signals by coefficients produced by the coefficient generators. Based on the magnitude of the undesired coefficient, certain states of the coefficient generators may be repeated or skipped to adjust the time and frequency domain of the output from the digital filter.