Abstract: A computer system comprising a display monitor including an audio function and a computer coupled to the display monitor including a computer controller for controlling the audio function in the monitor. The computer is operable in a computer mode, a television mode, and a combination computer/television mode for displaying computer and television information on the monitor. The system determines whether the monitor includes a controller for controlling its audio function. Based upon this determination, the system controls the audio function with the audio controller in the monitor if the monitor includes such a controller or, alternatively, with the computer controller if the monitor does not have such a controller.

Abstract: A first-in-first-out (FIFO) memory system. The FIFO memory system contains a first fall-through FIFO having an input and an output. A pointer-based FIFO having an input and an output, wherein the input of the pointer-based FIFO is connected to the output of the first fall-through FIFO. The FIFO memory system also includes a second fall-through FIFO having an input and an output, wherein the input of the second fall-through FIFO is connected to the output of the pointer-based FIFO, wherein data placed into the input of the first fall-through FIFO appears at the output of the second fall-through FIFO in a first-in-first-out basis.

Abstract: In a library apparatus, a transport device for transporting a medium to a drive unit and inserting the medium into the drive unit has a function of issuing, via a SCSI bus, a command to devices connected to the SCSI bus. Upon the power-on, the initiator function issues an inquiry command to the devices connected to the SCSI bus so that the number and types of the drive units installed in the library apparatus can be recognized based on inquiry data sent by the devices. In accordance with the number and types of the drive units installed in the library apparatus recognized, the transport device is controlled to properly transport the medium to the drive unit and insert the medium into the drive unit.

Abstract: A method and system for simulating auto-init DMA transfers to peripheral devices that do not support system DMA. To simulate auto-init mode DMA, a device driver monitors and responds to activity on the DMA channel when the application program specifies auto-init mode DMA. Data in a buffer is transferred to the peripheral device in small amounts called bursts. Several bursts comprise a block, and the end of each block must coincide with the end of a burst. When a burst is transferred from the buffer to the peripheral device, the peripheral device generates a physical interrupt. The device driver intercepts the physical interrupt and sends a virtual interrupt to the application program only when the physical interrupt is received for a burst that ends at the end of a block. In this manner, the application program is informed that it can again write data into the buffer for subsequent transfer to the peripheral device.

Abstract: A conventional computer is coupled to an analog telephone transmission link by means of an analog/digital conversion interface adapter. Modem transmission is accomplished by performing the modulation and demodulation functions digitally in the computer's existing processor which executes programs which transfer data between the computer's memory and the interface adapter. Using the same interface adapter and existing processor, the arrangement may be used to send and receive images in the form of standard V.29 format facsimile data, to send and receive data operating as a synchronous IBM 3270 compatible terminal device, or to record and play back conventional voice transmissions rather than data to implement a telephone answering, voice message handling, and telemarketing systems.

Abstract: A data transfer method with peripheral precharge wherein a starting portion of an output data block targeted for a peripheral is transferred to an output buffer for the peripheral using programmed I/O or slave cycles and wherein a virtual address of the output data block is translated into a physical address while the peripheral begins transferring the starting portion from the output buffer and over an output path. A direct memory access operation by the peripheral transfers a remainder portion of the output data block into the output buffer.

Abstract: A prefetch apparatus optimizes bandwidth in a computer network by prefetch accessing data blocks prior to their demand in an ATM network thereby effectively reducing memory read latency. The method of the preferred embodiment includes the steps of: 1) computing a prefetch address of a next sequential data block given an address of a requested data block; 2) comparing a current request address against a previously computed prefetch address; and 3) generating a hit/miss indication corresponding to whether the current request address matches the previously computed prefetch address.

Abstract: A method is disclosed for giving a host CPU direct access to the address space of an embedded microprocessor in a multifunction controller. The data path of the multifunction controller chip is modified to enable this direct access.

Abstract: An automated method to determine the real-time status of a currently running batch program on a mainframe computer system. Output from a tape management reporting system is processed so that relevant information pertaining to the progress of a currently running batch program is extracted and derived therefrom. New reports are generated that reveal the current status of the batch program in terms of the processing time of the dataset associated with the batch program. The new reports disclose useful status information such as the total number of volumes that comprise the dataset, the sequence number of the current volume being processed, the amount of time the currently running batch program used to process the volumes already processed, and the amount of time the previously run batch program used to process the volumes that have not yet been processed by the currently running batch program.

Abstract: A distributed direct memory access (DMA) architecture where greater than seven DMA channels are provided and utilized. Alternative methods are disclosed for paging or swapping DMA channels so that more than seven may exist in a computer system, but only seven may be available at a time to remain compatible with conventional DMA controller software. In one method, channels may be assigned identical addresses, with one enabled at one time. In another method, channels are assigned unique addresses but the DMA master addresses only a subset of of the total number of channels so that up to seven are available to compatible software at any one time.