Abstract: An insulating substrate (1) has insulative ceramic layers (2, 3) laid one upon another, an intermediate layer (4) made of a material that is different from a material of the ceramic layers and arranged between adjacent ones of the ceramic layers to join the adjacent ceramic layers to each other, a first conductive layer (5) joined to the top surface of a top one of the ceramic layers, and a second conductive layer (6) joined to the bottom surface of a bottom one of the ceramic layers. Even if any one of the ceramic layers has strength lower than design strength and causes a breakage due to, for example, thermal stress, the remaining ceramic layers are sound to secure a specified breakdown voltage for the insulating substrate.

Abstract: A liquid crystal display has a pad structure. The pad structure includes at least one pad formed on a substrate, an insulating film formed on the pad, and at least one conductive layer connected to the pad through contact holes defined through the insulating film. The insulating film covers side surfaces of the pad and a portion of the substrate adjacent to the side surfaces of the pad.

Abstract: An inverse-T transistor is formed by a method that decouples the halo implant, the deep S/D implant and the extension implant, so that the threshold voltage can be set by adjusting the halo implant without being affected by changes to the extension implant that are intended to alter the series resistance of the device. Formation of the inverse-T structure can be made by a damascene method in which a temporary layer deposited over the layer that will form the cross bar of the T has an aperture formed in it to hold the gate electrode, the aperture being lined with vertical sidewalls that provide space for the ledges that form the T. Another method of gate electrode formation starts with a layer of poly, forms a block for the gate electrode, covers the horizontal surfaces outside the gate with an etch-resistant material and etches horizontally to remove material above the cross bars on the T, the cross bars being protected by the etch resistant material.

Abstract: A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for the mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200–250° C.).

Abstract: Disclosed herein are a junction where electrical interconnects on a semiconductor substrate intersect and a method of manufacturing a junction where electrical interconnects on a semiconductor substrate intersect is disclosed. In one embodiment, the junction includes a portion of at least one current providing electrical interconnect having a length parallel to a longitudinal axis thereof and configured to provide a flow of electrical current. In addition, the junction includes a portion of at least one current receiving electrical interconnect having a length parallel to a longitudinal axis thereof and configured to intersect with the at least one current providing interconnect at the junction in order to receive the flow of electrical current from the at least one current providing interconnect.

Abstract: A polishing method and a polishing apparatus by which excess portions of a metallic film 18 can be removed easily and efficiently in planarizing the metallic film 18 by polishing and which is high in accuracy of polishing, are provided. Also, a method of manufacturing a semiconductor device by use of the polishing method and the polishing apparatus is provided. A substrate 17 provided with the metallic film 18 and a counter electrode 15 are disposed oppositely to each other in an electrolytic solution E, an electric current is passed to the metallic film 18 through the electrolytic solution E, and the surface of the metallic film 18 is polished with a hard pad 14.

Abstract: A semiconductor package including a flexible multichip module having multiple chips on flexible appendages with the flexible appendages folded so that the semiconductor chips are arranged in aligned and stacked positions.

Abstract: A vapor deposition shadow mask system includes a number of series connected vacuum vessels each having a material deposition source and shadow mask positioned therein. A substrate is translated along a path that has a longitudinal axis that extends through the vacuum vessels. Centers of shadow masks in first and second vacuum vessels are offset laterally on opposite sides of the longitudinal axis. The system is operative for depositing material on a second area of the substrate via the material deposition source and shadow mask in the second vacuum vessel in a manner that overlaps a portion of the material deposited on a first, adjacent area of the substrate via the material deposition source and shadow mask in the first vacuum vessel.

Abstract: A transistor includes a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, wherein the channel and at least one of the source or the drain are separated by an interface layer so as to form a channel-interface layer-source/drain junction in which a Fermi level of the semiconductor channel is depinned in a region near the junction and the junction has a specific contact resistance of less than approximately 1000 ?-?m2. The interface layer may include a passivating material such as a nitride, a fluoride, an oxide, an oxynitride, a hydride and/or an arsenide of the semiconductor of the channel. In some cases, the interface layer consists essentially of a monolayer configured to depin the Fermi level of the semiconductor of the channel, or an amount of passivation material sufficient to terminate all or a sufficient number of dangling bonds of the semiconductor channel to achieve chemical stability of the surface.

Abstract: A film carrier tape for mounting electronic devices thereon has a tin-bismuth alloy deposit in which the bismuth content in the deposit is substantially uniform along a thickness direction thereof. The film carrier tape can be produced by plating at least a part of a wiring pattern with a tin-bismuth alloy and washing the tin-bismuth alloy deposit formed by plating with a water-ejecting washing nozzle within 6 seconds after the plating is completed. A plating apparatus for use in the above production includes a washing nozzle for washing the film carrier tape within 6 seconds after the film carrier tape has exited a plating tank.

Abstract: The present invention is a method of performing processing for a substrate including the step of carrying the substrate, which has been pre-treated, to a heat treatment unit for heating the substrate, prior to supplying a treatment solution to the substrate to perform solution treatment, in which the carrying is performed such as to fix a period after the pretreatment for the substrate is completed and before it is carried to the heat treatment unit. According to the present invention, for example, in a lithography process, the substrate is carried such as to fix the period after exposure processing that is the pretreatment and before the substrate is carried to the heat treatment unit where heat treatment that is the following treatment is performed, whereby the degrees of chemical reaction of coating films by the exposure processing become uniform between the substrates.

Abstract: Chemical vapor deposition processes are employed to fill high aspect ratio (typically at least 3:1), narrow width (typically 1.5 microns or less and even sub 0.13 micron) gaps with significantly reduced incidence of voids or weak spots. This deposition process involves the use of hydrogen and a phosphorus dopant precursor as process gasses in the reactive mixture of a plasma containing CVD reactor. The process gas also includes dielectric forming precursor molecules such as silicon and oxygen containing molecules.

Abstract: A method of forming a micro groove structure according to the invention has the steps of: (a) forming a mask pattern on a substrate capable of being subjected to dry etching; (b) dry etching the substrate having the mask pattern formed thereon; (c) vapor-phase forming a thin film of a masking material for the dry etching, on a non-etched surface portion of the substrate after the dry etching; and (d) dry etching the substrate having the thin film formed thereon. The steps (a) to (d) are carried out successively.

Abstract: Spaces in a nanostructure can be filled with an organic material while in the solid state below Tm (without heating) by exposing the organic material to solvent vapor while on or mixed with the nanostructured material. The exposure to solvent vapor results in intimate contact between the organic material and the nanostructured material without having to expose them to possibly detrimental heat to melt in the organic material. Solution processing methods need only to be employed to create bulk films while organic material infiltration can take place in the solid state after depositing the film.

Abstract: The electronic device is formed in a die including a body of semiconductor material having a first face covered by a covering structure and a second face. An integral thermal spreader of metal is grown galvanically on the second face during the manufacture of a wafer, prior to cutting into dice. The covering structure comprises a passivation region and a protective region of opaque polyimide; the protective region and the passivation region are opened above the contact pads for the passage of leads.

Abstract: A method, system and materials for use in hydrogen gettering in conjunction with microelectronic and microwave components that are generally hermetically sealed in an enclosure typically referred to as a “package”. Gettering materials that can be used include titanium with or without a hydrogen permeable coating or covering, alloys of zirconium-vanadium iron and zeolites and several ways to apply these materials to the package. In addition, the hydrogen permeable material can be used over a vent from the interior of the package to the exterior wherein hydrogen will escape from the package interior when the hydrogen concentration within the package is greater than without the package.

Abstract: A method of providing a regular outline in a useful layer of material that is transferred from a source substrate onto a support substrate during the fabrication of a composite substrate for subsequent use in electronics, optics, or optoelectronics. The technique includes providing a shoulder on a front face of one of the source or support substrates about its periphery. The shoulder defines an inner projecting zone that has a top face, a sidewall and a regular outline. Next, the method includes molecularly bonding the top face of the projecting zone to a receiving face of the other of the source or support substrates, and removing a portion of the projecting zone from the source substrate to provide the useful layer having the regular outline on the support substrate.

Abstract: A new method to form an integrated circuit device is achieved. The method comprises forming a dielectric layer overlying a semiconductor substrate. An intrinsic semiconductor layer is formed overlying the dielectric layer. The intrinsic semiconductor layer is patterned. A p+ region is formed in the intrinsic semiconductor layer. An n+ region is formed in the intrinsic semiconductor layer. The p+ region and said n+ region are laterally separated by an intrinsic region to thereby form a PIN diode device. A source region and a drain region are formed in the semiconductor substrate to thereby complete a MOSFET device. The PIN diode device is a gate electrode for the MOSFET device.