Abstract: In the present invention, a modulation level estimation unit calculates the square error of the minimum value of distances between each signal point received at a modulation level ML and the signal point of a received signal at each modulation level ML. A received power measurement unit measures the received power level of the received signal. A modulation level estimation unit calculates the value obtained by multiplying the square error calculated at each modulation level ML, by a weighted calculation from both a threshold power level for switching the modulation level ML and the received power level as a likelihood value at each modulation level ML. Then, the modulation level estimation unit estimates a modulation level ML corresponding to the maximum likelihood value of all the likelihood values at the modulation level ML as a modulation level ML of the received signal, without transmitting any codewords on the used modulation level.

Abstract: A method and system for performing a timing recovery acquisition of a sinusoidal preamble with reduced loop latency by effectively bypassing the FIR filter out of the timing loop. The method is implemented by estimating the FIR filter's (201) phase shift through knowing its coefficients a priori while also determining the phase error at the FIR filter's input. Because of the non-symmetric settings of the coefficients the phase shift through the FIR may not be zero. It reduces the latency of a non-data tracking timing loop by eliminating latency due to the FIR filter (201) itself. The coefficients can be either programmed in memory (205) or adapted as part of an LMS application. The estimate avoids the use of multiply operations, using add operations and a single divider. The estimated partial phase errors are then summed in a “FIR bypass-mode” phase detector (204) yielding total phase shift.

Abstract: A communication system provides robust, short range radio communications between battery operated devices by using ON-OFF-KEYED (OOK) modulation and either frequency shift keyed (FSK) modulation or pulse position/width modulation (PPM/PWM), in combination with a prescribed communications protocol. The system transmitter requires no local oscillator and is only active during actual communication, so that its current drain is not a significant factor in total battery life. Also, the receiver is active for only a small fraction of time. The need for large, complex and expensive filters is minimized by using a single IF band-pass filter in active form or passively in the form of a low cost ceramic filter such as those used in inexpensive transistor radios. The digital transmitter and receiver portions of the system are implemented by low cost, and ultra low power CMOS logic.

Abstract: A digital communications receiver is provided with a PSK demodulator and a soft-decision decoder. The PSK demodulator is configured to accept a receive signal and responsively produce quantized baseband signal components which include a quantized radial component RQ and a quantized angular component &thgr;Q. The soft-decision decoder is coupled to the PSK demodulator to receive the quantized baseband signal components and is configured to convert the quantized signal components into decoded information bits. The soft-decision decoder preferably uses a squared Euclidean distance metric calculation for the decoding process. Using polar coordinate quantization provides an improved performance relative to Cartesian coordinate quantization. A new distance metric for TCM decoding is also provided which requires less implementation complexity than a standards Euclidean distance metric calculation, and which suffers no significant performance loss.

Abstract: The apparatus and method for estimation and minimization of the residual multipath error signal are disclosed. The reduction of the multipath error signal is achieved by using the weighted or modified tracking. The estimation and minimization of the reduced multipath error signals is achieved by using the generator of additional modified or weighted signals.

Abstract: In a transceiver unit including an adaptive equalizer filter unit, apparatus is provided for reducing or compressing the number of bits representing an error signal. The apparatus replaces a plurality of the most significant logic signal bits with a single bits while transferring the sign logic signal bit and the logic signal bits of lesser significance unchanged. Because of the reduction in the number of logic signal bits, the number of components implementing the multiplier unit in the adaptive filter unit can be reduced (i.e., in each stage of the adaptive filter). The reduction of the apparatus implementing the processing the error signal results in the same equilibrium value of the error signal, however, the time to reach this equilibrium value is increased.