Abstract: A resistive network is coupled to a reference source for providing a plurality of reference signals. A comparator/multiplexer section compares a comparison signal against the reference signals, selects one of the reference signals and produces a code. An amplifier provides the comparison signal in response to the ADC input signal and subsequently in response to a signal difference between the ADC input signal and selected reference signal. Two codes are encoded and added in an adder/accumulator for providing the output code of the ADC.

Abstract: A true N-bit digital-to-analog converter (DAC), i.e. a DAC the absolute accuracy error of which is less than 1 LSB (or .+-.1/2 LSB), can be composed of easy obtainable and low-priced components. The DAC distinguishes a very fast, highly accurate, high resolution conversion of a digital input code into an equivalent voltage or current.Two or more DACs are cascaded in order to attain a high resolution. Only one ROM and an associated DAC are necessary to obtain an accuracy error of less than 1 LSB, in consequence of the increased resolution. The final trimming can be conducted in packaged form of the device through the ROM programming.For example, a true 16-bit DAC can be composed of three equal true 8-bit DACs, wherein their absolute accuracy error must be less than 0.992 LSB. A ROM with the storage capacity of only 256 bytes is necessary.

Abstract: In a device which is for use in a receiver of a multivalued digital communication system and which includes a reference voltage producing circuit (51) for producing signal discriminating reference voltages and signal regenerating reference voltages related to one another, a level discriminating circuit (31) for discriminating a multivalued received signal with reference to the signal discriminating reference voltages to produce a local encoded signal, a signal decoding circuit (32) for decoding the local encoded signal into a decoded signal, a signal regenerating circuit (33) responsive to the local encoded signal for regenerating a multivalved regenerated signal having the signal regenerating reference voltages, a comparator (34) for comparing the received and the regenerated signals to produce a result of comparison, and an integrator (35) for integrating the result of comparison to produce a result of integration, the signal discriminating and regenerating reference voltages are regulated by the result of

Abstract: There is provided a digitally controlled first order hold circuit and waveform synthesizer for digitally controlling the representation of a function over an approximation interval. In accordance with the operation of the invention, the first order hold circuit and waveform generator receives a digital data input signal which contains initial condition data, up/down data, and slope data for the approximation interval. The initial condition data is loaded into an up/down counter which is incremented using counting data at a rate depending on the value of the slope data and in a direction depending on the value of the up-down data. In order to minimize delays arising from data acquistion, two frequency synthesizer circuits are provided such that one frequency synthesizer provides counting data while the other frequency synthesizer receives slope data. During alternating intervals, the other frequency synthesizer circuit provides counting data while the other circuit receives slope data.

Abstract: A digital-to-analog converter of current segment type, having a plurality of first variable current sources and a second variable current source of the same structure as the first variable current sources. The converter further comprises a comparator. The comparator compares a voltage corresponding to the output current of the second variable current source with a reference voltage. The difference between these compared voltages is used to determine the output currents of the first variable current sources.

Abstract: A distortion reduction circuit for a digital to analog converter, comprising a bit detection circuit for detecting the logic value of any bit from input data thereto, a synchronizing circuit for synchronizing the output from the bit detection circuit with the analog output from the converter, and an adding and subtracting circuit for converting the value of an output voltage from the synchronizing circuit to a direct current voltage having any level. The output from the adding and subtracting circuit is arranged to be added to the analog output from the digital to analog converter.