Abstract: Various aspects of the disclosed technology relate to machine learning-based chain diagnosis. Faults are injected into scan chains in a circuit design. Simulations are performed on the fault-injected circuit design to determine test response patterns in response to the test patterns which are captured by the scan chains. Observed failing bit patterns are determined by comparing the unloaded test response patterns with corresponding good-machine test response patterns. Bit-reduction is performed on the observed failing bit patterns to construct training samples. Using the training samples, machine-learning models for faulty scan cell identification are trained. The bit reduction comprises pattern-based bit compression for good scan chains or cycle-based bit compression for the good scan chains. The bit reduction may further comprise bit-filtering. The bit-filtering may comprises keeping only sensitive bits on faulty scan chains for the training samples construction.

Abstract: Systems and methods for automatic test pattern generation (ATPG) for parametric faults are described. A model may be constructed to predict a measurement margin for an integrated circuit (IC) design based on a random sample of random variables. A set of failure events may be determined for the IC design using the model, where each failure event may correspond to a set of values of the random variables that is expected to cause a metric for the IC design to violate a threshold.

Abstract: The present disclosure advantageously provides a system and a method for skipping recurrent neural network (RNN) state updates using a skip predictor. Sequential input data are received and divided into sequences of input data values, each input data value being associated with a different time step for a pre-trained RNN model. At each time step, the hidden state vector for a prior time step is received from the pre-trained RNN model, and a determination, based on the input data value and the hidden state vector for at least one prior time step, is made whether to provide or not provide the input data value associated with the time step to the pre-trained RNN model for processing. When the input data value is not provided, the pre-trained RNN model does not update its hidden state vector. Importantly, the skip predictor is trained without retraining the pre-trained RNN model.

Abstract: Methods, systems, and non-transitory computer readable medium are described for generating assessment maps for corrective action. A method includes receiving a first vector map including a first set of vectors each indicating a distortion of a particular location of a plurality of locations on a substrate. The method further includes generating a second vector map including a second set of vectors by rotating a position of each vector in the first set of vectors. The method further includes generating a third vector map including a third set of vectors based on vectors in the second set of vectors and corresponding vectors in the first set of vectors. The method further includes generating a fourth vector map by subtracting each vector of the third set of vectors from a corresponding vector in the first set of vectors. The fourth vector map indicates a planar component of the first vector map.

Abstract: A rechargeable battery short-circuit early detection device that detects a short-circuit in a rechargeable battery includes one or more processors connected to a current sensor that detects a charging current of the rechargeable battery, wherein the one or more processors are programmed to: while the rechargeable battery is being charged, receive a current signal indicating the charging current from the current sensor; detect a temporal change in the charging current indicated by the current signal; determine, when the charging current increases over time, that there is a possibility that the rechargeable battery has short-circuited; and output data indicating a determined result.

Abstract: A controlled quantum logic gate implements a n?1 qubit controlled Z gate function based on n qubits and an ancilla qubit, wherein n is greater than 3. The quantum logic gate includes a plurality of leading gates that operate on the at least one ancilla qubit to generate an ancilla qubit state in response to an initial state of the ancilla bit and each of the n qubits. A measurement operates on the ancilla qubit state to generate a classical ancilla bit state. At least one following gate includes at least one controlled Z gate equivalent that operates under control of at least one of the n qubits and further under control of the classical ancilla bit state to selectively apply a phase adjustment to at least another one of the n qubits.

Abstract: Computer implemented methods and computer program products have instructions for generating transfer functions that relate segments on lithography photomasks to features produced by photolithography and etching using such segments. Such methods may be characterized by the following elements: (a) receiving after development inspection metrology results produced from one or more first test substrates on which resist was applied and patterned using a set of design layout segments; (b) receiving after etch inspection metrology results produced from one or more second test substrates which were etched after resist was applied and patterned using said set of design layout segments; and (c) generating the transfer function using the set of design layout segments together with corresponding after development inspection metrology results and corresponding after etch inspection metrology results.

Abstract: A hybrid quantum-classical (HQC) computer prepares a quantum Boltzmann machine (QBM) in a pure state. The state is evolved in time according to a chaotic, tunable quantum Hamiltonian. The pure state locally approximates a (potentially highly correlated) quantum thermal state at a known temperature. With the chaotic quantum Hamiltonian, a quantum quench can be performed to locally sample observables in quantum thermal states. With the samples, an inverse temperature of the QBM can be approximated, as needed for determining the correct sign and magnitude of the gradient of a loss function of the QBM.

Abstract: An optical proximity correction method includes extracting first patterns from a pattern mask, performing lithography on at least a part of the first patterns to form first-first patterns, forming the first-first patterns at positions where the first patterns are formed, and performing correction on the pattern mask on which the first-first patterns are formed.

Abstract: In an embodiment, a correlated forecast is computer generated by a processor that receives input data for historic values of a first input variable, creates forecast data for future values of the first input variable using the historic values of the first input variable, generates diagnostic data based on a diagnostic analysis of the forecast data, creates a first diagnostic variable that includes a first diagnostic value from a first cognitive process, generates a feature vector based on a second cognitive process that determines the feature vector by identifying a correlation between the first diagnostic variable and a second diagnostic variable, and generates a final forecast using the feature vector as an input for a cognitive forecasting process, where the first cognitive process determines the first diagnostic value based on the diagnostic data.

Abstract: Aspects of the invention provide means for addressing layout retargeting shortfalls. Initially, an original design shape in the layout is allowed to be simulated by process simulation to form process simulation contours. A polygon is then fitted to the process simulation contours to form a fitted simulated shape. Subsequently, whether the fitted simulated shape differs from the original design shape is detected. The process simulation may reflect the changes to the layout that occur at a foundry as part of a retargeting process. Advantageously, addressing a layout for retargeting shortfalls in accordance with aspects of the invention is likely to result in manufactured semiconductor devices having higher yields and reliability than those produced from a like layout that is not addressed in this manner.

Abstract: In an optimization apparatus, a computing unit searches for the ground state of an Ising model generated by converting an optimization problem to be solved, based on Ising model information representing the Ising model and a temperature parameter. A control unit determines the minimum value of the temperature parameter, based on a resolution in energy of the computing unit for the Ising model and a first reference value indicating an acceptance probability of state transition in the Ising model at the minimum value, determines a maximum amount of change in energy, based on the Ising model information, determines the maximum value of the temperature parameter, based on the determined maximum amount of change in energy and a second reference value that is greater than the first reference value and indicates the acceptance probability at the maximum value, and sends the minimum and maximum values to the computing unit.

Abstract: A lithography process is described by a design for a lithographic mask and a description of the lithography configuration, which may include the lithography source, collection/illumination optics, projection optics, resist, and/or subsequent fabrication steps. The actual lithography process uses a lithographic mask fabricated from the mask design, which may be different than the nominal mask design. A mask fabrication model models the process for fabricating the lithographic mask from the mask design. Typically, this is an electron-beam (e-beam) process, which includes e-beam exposure of resist on a mask blank, processing of the exposed resist to form patterned resist, and etching of the mask blank with the patterned resist. The mask fabrication model, usually in conjunction with other process models, is used to estimate a result of the lithography process. Mask correction is then applied to the mask design based on the simulation result.

Abstract: The present disclosure discloses a processing element and a neural processing device including the processing element. The processing element includes a weight register configured to store a weight, an input activation register configured to store an input activation, a flexible multiplier configured to receive a first sub-weight of a first precision included in the weight, receive a first sub-input activation of the first precision included in the input activation, and generate result data by performing multiplication calculation of the first sub-weight and the first sub-input activation as the first precision or a second precision different from the first precision according to the first sub-weight and the first sub-input activation and a saturating adder configured to generate a partial sum by using the result data.

Abstract: This invention relates to a mobile charging unit (1), particularly for one or more electric vehicles (4), of the type including rechargeable batteries (41), comprising a mobile charging vehicle (2), and a charging apparatus (3), installed on said charging vehicle (2), having, in turn: an energy accumulation group (5), equipped with accumulators (51) for containing energy for charging said electric vehicles (4); an inverter (6), connected to said accumulators (51), comprising a DC-AC-DC converter (62) to convert the direct current coming from said accumulators (51) into alternating current, wherein said inverter (6) is connectable to an alternating current network (9) and is adapted to transform the alternating current of said alternating current network (9) into direct current for charging said accumulators (51); and an internal control system (7), connected to said inverter (6), adapted to control the operation of said inverter (6); said charging apparatus (3) is characterised in that said inverter (6) furth

Abstract: Embodiments of the present invention provide methods, computer program products, and systems. Embodiments of the present invention can be used to partition an area into zones, wherein each zone includes one or more delivery mechanisms and each delivery mechanism include one or more portions that are capable of charging an electric vehicle. Embodiments of the present invention can be used to, in response to receiving a request to charge, reserve a portion of a delivery mechanism for a fixed period of time based on available capacity of the delivery mechanism and need of the requesting electric vehicle. Embodiments of the present invention can be further used to modify the fixed period of time based on real time use of the delivery mechanism.

Abstract: A power planning phase module, a placement phase module, and a routing phase module are provided that can replace, supplement, or enhance existing electronic design automation (EDA) software tools. The power planning phase module adds distributed power sources and a network of switching elements to the power frame or ring assigned to regions of a chip (that may be identified during a floor planning stage). The placement phase module optimizes a number and type of cells attached to each power source of the distributed power sources already added or to be added during the power planning phase. The routing phase module optimizes routing length to, for example, mask power consumption.

Abstract: The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.

Abstract: A device having a function of simultaneously charging and backing up data is provided. The device includes a transmission interface, a power supply circuit, a storage circuit, and a main control circuit. The transmission interface is connected to an electronic device. The power supply circuit is configured to supply power to the electronic device to charge the electronic device. The storage circuit is configured to access data of the electronic device, or to provide data stored in the storage circuit to the electronic device. The main control circuit is connected to the transmission interface, the power supply circuit and the storage circuit. The main control circuit is configured to control the power supply circuit to supply the power to the electronic device and the storage circuit to back up the data simultaneously.

Abstract: The present disclosure relates to methods and systems for management and control of interconnected energy storage modules, such as battery packs, that can form a larger energy storage system. The disclosure also relates to methods and system for the measurement of cell impedances in a battery pack in-situ and on-line and using active balancing circuits that may already be present in the battery pack. The methods and systems can inject disturbances of different frequencies and measure impedance by using the active balancing circuits present in the battery pack, which can transform an active balancer into a dual active balancer and impedance measurement system. The speed up of impedance measurement energy storage modules can be accomplished by using multi-tone, orthogonal or spread spectrum waveforms applied simultaneously on all or a sub-set of the active balancer circuits in an active balancer.