Abstract: A wireless device, method, and signal for use in communication of a wireless packet between transmitting device and a wireless receiving device via a plurality of antennas, wherein a signal generator generates wireless packet including a short-preamble sequence used for a first automatic gain control (AGC), a first long-preamble sequence, a signal field used for conveying a length of the wireless packet, an AGC preamble sequence used for a second AGC to be performed after the first AGC, a second long-preamble sequence, and a data field conveying data. The AGC preamble sequence is transmitted in parallel by the plurality of antennas.

Abstract: A circuit and method for adaptively controlling an equalizer circuit to reduce intersymbol interference at low frequencies relative to a transmit frequency of an input signal from a transmitter. The input signal is converted into a data signal by a receiver. At least one delayed data signal is formed by delaying the data signal by at least one unit interval (UI) beyond a length of a decision feedback equalizer (DFE) in the receiver. An error signal is formed by comparing the input signal to a threshold value. An error signal sample is correlated with at least one delayed data signal sample to determine whether to adjust a control coefficient of the equalizer. Thus the equalizer is controlled as if the DFE had at least one additional tap.

Abstract: Embodiments herein include a replica communication path and monitor circuit to provide increased common mode transient immunity. As its name suggests, the monitor circuit monitors the replica communication path and produces an adjustment signal (common mode transient adjustment signal) to cancel presence of a common mode transient signal in one or more other communication paths conveying data signals.

Abstract: A data collection system includes a plurality of sensor modules each provided with a sensor unit, and a data collecting device. The data collecting device (200) is provided with: a clock output unit (201) which outputs a clock signal; an enable signal output unit (202) which outputs to a prescribed sensor module (100) an enable signal at intervals equal to or greater than the number of clock signals corresponding to the number of sensor modules (100); a counter (203) which counts the number of clock signals; and a sensor signal input unit (205) into which data output by the sensor modules (100) is input via a bus line, and which records said data in association with the count value.

Abstract: System and method for dimension reduction and for channel and interference condition feedback in a Multi-User Multiple-Input-Multiple-Output (MU MIMO) wireless communication system. The method for dimension reduction includes determining a number of virtual antennas, vk, for beamformees pertaining to a multi user (MU) transmission group, reducing the dimension of said matrix by selecting a sub-set of antennas or by Eigen mode selection and sending a reduced dimension candidate transmit beamforming matrix or an effective channel matrix to a beamformer. The method for channel and interference condition feedback Interference condition includes sending to a beamformee metric indicative of the interference level from other streams.

Abstract: A serial data receiver may include an edge detector and a digital integrator. The edge detector may be configured to provide one or more edge detection signals defining an edge detection indication in response to a comparison between two successive samples of a receiver input signal. The edge detection indication may represent a detected negative edge, a detected positive edge, or no detected edge. The digital integrator may be configured to provide a receiver output signal in response to integration of the one or more edge detection signals.

Abstract: An adaptive digital pre-distortion system includes a transmitting module and a receiving module. The transmitting module is configured to receive a first signal and includes a modulator, pre-distortion module, and transmitting circuit. The pre-distortion module is coupled to the modulator to perform a pre-distortion operation in accordance with the first modulation signal and generate a first pre-distortion signal. The transmitting circuit generates a first transmitted signal in accordance with the first pre-distortion signal. The receiving module is configured to receive the first transmitted signal and includes a receiving circuit, demodulator, and prediction module.

Abstract: Isolation circuits for digital communications and methods to provide isolation for digital communications are disclosed. An example isolation circuit includes an isolation barrier, a burst encoder in a first circuit, and an edge pattern detector in a second circuit. The example isolation barrier electrically isolates the first circuit from the second circuit. The example burst encoder generates a first pattern in response to receiving a rising edge on an input signal and generates a second pattern in response to receiving a falling edge on the input signal. The example edge pattern detector detects the first pattern or the second pattern received from the burst encoder via the isolation barrier, sets an output signal at a first signal level in response to detecting the first pattern, and sets the output signal at a second signal level in response to detecting the second pattern.

Abstract: Voltage regulator circuits for wireless devices are provided. In some implementations, a transceiver module includes a transceiver circuit that generates a radio frequency (RF) signal, a power amplifier circuit that receives the RF signal and generates an amplified RF signal, and a voltage regulator circuit that receives an input voltage and provides a desired voltage to the power amplifier circuit. The voltage regulator circuit is operable in a regulation mode in which the desired voltage includes a regulated voltage and in a bypass mode in which the desired voltage includes a bypass voltage. The voltage regulator circuit includes a field-effect transistor (FET) electrically connected between the input voltage and the desired voltage, an amplifier that controls the FET, and a voltage generator that receives the input voltage and biases the amplifier.

Abstract: A method includes communicating data in a channel. Received symbols for the data correspond to points of a received symbol space respectively. First and second dimensions of the received symbol space correspond to a real part and an imaginary part of the received symbols respectively. A first received symbol for the data is obtained. A first region of the received symbol space for the first received symbol is determined. A first regression model associated with the first region and a first bit of the first received symbol is retrieved from a storage. The first regression model includes a plurality of regressors. A first log-likelihood ratio (LLR) for the first bit of the first received symbol is estimated using the first regression model.

Abstract: A receiving circuit includes a receiver configured to receive a signal, a detector configured to detect arrival of a reception signal based on a signal received by the receiver, a buffer configured to store therein data corresponding to the reception signal, a demodulation processor configured to demodulate data to be supplied, and a controller configured to store the data corresponding to the reception signal in the buffer when the detector does not detect the arrival of the reception signal, and to supply the data stored in the buffer to the demodulation processor when the detector detects the arrival of the reception signal.

Abstract: Systems and methods for phase detection are disclosed. Phase alignment between first and second clock signals is detected using a comparison of outputs from a collapsible pipeline and a non-collapsible pipeline.

Abstract: An example method of clock and data recovery in a receiver includes generating data samples and crossing samples of a received signal based on a data clock signal and a crossing clock signal, respectively, which are derived from a sampling clock signal; adjusting a phase of the sampling clock signal using a clock and data recovery (CDR) circuit based on the data samples and the crossing samples; adjusting relative phase between the data clock signal and the crossing clock signal from a first phase difference to a second phase difference that is less than ninety degrees; and reverting the relative phase between the data clock signal and the crossing clock signal to the first phase difference after a threshold time period.

Abstract: This invention discloses apparatus and methods for detecting transmit symbols from the receiving waveform samples at the receiver side for communications systems. The receiving waveform samples are corrupted by channel and noise effects and the detection is carried out with a maximum likelihood optimality criterion. This invention utilizes a successive linear constraint exchange scheme that formulates a sequence of linearly constrained minimization subproblems to allow the solutions to these subproblems, combined with certain quantization and mapping operations, to converge to the optimal maximum likelihood estimate. This invention is applicable to any digitally modulated communications systems, including but not limited to Multiple Input Multiple Output (MIMO) communications systems.

Abstract: The invention relates to a method for controlling digital data transmission in a remote-reading apparatus including a plurality of metering devices, each equipped with a radiofrequency module for communicating with a radiofrequency transmission/reception device of a gateway system of the apparatus, the method comprising a step of transmitting a digital signal from the radiofrequency module to the radiofrequency transmission/reception device and/or from the radiofrequency transmission/reception device to the radiofrequency module, the transmission being carried out via a carrier modulated by frequency shift modulation, the method being characterized in that the frequency shift modulation has a modulation index strictly equal to an integer value divided by two, and in that it includes a step of receiving the signal transmitted according to the modulation, comprising operations of generation of a synchronization signal synchronized with the received signal and synchronous detection of the received signal using t

Abstract: A method of enabling a communication channel between a first communication circuit and a second communication circuit is described. The method comprises establishing a communication link according to a communication protocol between the first communication circuit and the second communication circuit, wherein the communication protocol enables the transmission of data between the first communication circuit and the second communication circuit at a standardized data rate; determining a standardized data rate for which the communication link between the first communication circuit and the second communication circuit fails to meet a predetermined quality threshold; and establishing a communication link according to the communication protocol at a non-standardized data rate below the determined standardized data rate.

Abstract: A method for reading a serial data stream in a piece of automation technology equipment includes encoding the data stream to include at least two symbols which are distinguishable by a time interval between two successive signal edges. The data stream is delivered to a read unit including a symbol recognition unit which associates a time sequence of the signal edges with a respective one of the symbols taking into account a period of time including a current symbol duration of one of the symbols to be currently associated and at least one old symbol duration of a preceding one of the symbols.

Abstract: A frequency-shift keying (FSK) demodulator includes a digital phase-locked loop (DPLL) based frequency estimator to convert a phase signal to a frequency signal, a frequency offset estimator to estimate and track direct current (DC) component of the frequency signal, and an average filter communicatively coupled to the frequency offset estimator to perform an accumulate-and-dump operation to improve a symbol-level signal to noise ratio (SNR) of the frequency signal.

Abstract: A plurality of receivers each having: an RF amplifier having an RFAMP input coupled to an antenna and having an RFAMP output; a capacitor having a CAP first side connected to the RFAMP output and a CAP second side; a passive mixer coupled to the RFAMP input, the CAP second side, and the output of a local oscillator phase shifter; an operational transconductor amplifier having an OTA input connected to the CAP second side and having an OTA output; a feedback resistor connected between the OTA input and the OTA output; a baseband transconductor having a BBGM input connected to the OTA input and a BBGM output; a cancelling transconductor having a CANCELLER output connected to the BBGM output and having a CANCELLER input; and an attenuator between the OTA output and the CANCELLER input, wherein the OTA output of each of the plurality of receivers are connected together.

Abstract: A modulator and demodulator pair may switch configurations without introducing errors as a result of the switch. Different configurations may, for example, correspond to different symbol rates and/or different amounts of controlled inter-symbol interference (ISI) introduced to the transmitted signal. For example, a first configuration may use be a near-zero ISI configuration (e.g., using Nyquist signaling) and a second configuration may introduce a significant (e.g., amount that would result in errors above a desired threshold if demodulation relied on symbol-by-symbol slicing) but controlled amount of ISI (e.g., using partial response or faster-than-Nyquist-rate signaling). Switching between modulator/demodulator configurations may be needed to maintain a stable link in the case of dynamic channels. At any given time, a modulator and demodulator pair may, for example, switch to a configuration that provides maximal throughput for the current channel conditions.