Abstract: A system and method is provided for optimizing a laser light fractionation during photodynamic therapy of a tumor. The tumor is destroyed through the production of singlet oxygen and successful photodynamic therapy treatment requires the maintenance of tumor oxygen above a specified critical level. Depending on the tumor, the photosensitizer concentration, and the laser fluence, sustained irradiation of the tumor will deplete the oxygen below the critical level. When the laser is turned off, oxygen diffuses into the tumor to provide sustained levels of singlet oxygen. The control system controls the operation cycle of the laser and the various surgical parameters. Data regarding the sensitizer, the laser characteristics, and the oxygen features of the tumor are input into the control system for simulation of the PDT treatment. As part of the simulation, the optimal fractionation cycle for the laser is predicted. The data may be adjusted for conducting additional simulations.

Abstract: A logic emulation system for emulating the operation of a circuit. A uniform routing architecture is provided where a first set of selectors (multiplexers) is coupled to a set of shift registers that are in turn coupled to a second set of selectors. The outputs of the second set of selectors are coupled to the inputs of the logic processors. The arrangement of first selectors coupled to shift registers coupled to second selectors coupled to logic processors ensures that uniform routing exists among all of the logic processors in the emulation system. This, in turn, provides a flat programming model so that compilation steps including technology mapping and scheduling are independent of each other, resulting in faster compile times.

Abstract: Disclosed is a data processing apparatus that has two or more internal SCSI devices, to include a SCSI controller, that can also accommodate eternal SCSI devices via a port connector and that can manage the ID numbers (identification numbers) of the internal SCSI devices separately from all the other SCSI devices without requiring any action by a user; and a method for controlling such a data processing apparatus. According to the present invention, ID numbers can be written into internal SCSI devices. ID numbers that do not collide with the ID numbers of the externally connected SCSI devices are assigned to the respective internal SCSI devices. The system can automatically write the ID numbers during the booting process or when the system configuration is physically changed. Even when there are SCSI hard disk drives installed both inside and outside the system, the ID numbers of the SCSI hard disk drives that are internally positioned can be read so that the internal SCSI hard disk drives can be designated.

Abstract: A method for translating a boolean function into a logic circuit using gates from a standard library is provided. The method includes the steps of translating the boolean function into a network comprising a plurality of sub-trees, where each of the sub-trees represents a portion of the function, and where each sub-tree includes a plurality of representations for that portion of the function. The plurality of representations are stored in an alterative logic diagram, which comprises a plurality of ugates. The ugates are data structures which define the inputs and the connectivity of the respective ugate in the sub-tree. The sub-tree is mapped to gates from the standard library by selecting the best sub-tree representation. Accordingly, an improved method of logic synthesis is provided that allows for the optimal representation to be provided by starting with a wider range of inputs to the mapping process.

Abstract: Method and a system for performing die yield prediction in cooperation with wafer scanning tools. A program analyzes data associated with defects on a wafer substrate, the substrate including multiple layers and multiple die. Files are read that contain defect data for selected layers of the substrate. The defect data includes defect type and defect size information. The defect data is then stacked to identify the layer of first occurrence of each defect and the number, i.e., count, of layers upon which it was redetected. A kill factor is then assigned to each of the defects according to a set of rules, each such rule specifying defect parameters that include layer of first occurrence, redetect count, defect size, and defect type. Failure probabilities, indicative of yield, are then computed for the defects according to the assigned kill factors. The failure probabilites are utilized to calculate the estimated die loss for selected wafers by layer and defect type.

Abstract: Functional blocks and block external wiring are roughly laid out in a semiconductor integrated circuit. The positions of cells in the functional blocks, block internal wiring and the block external wiring are determined through calculation of delay time as a sum of block external delay time and block internal delay time, so that clock skew of each cell is within a limited range and the delay time is within a desired range. Wiring patterns are formed in accordance with the determined wiring. In determining the positions of the cells in the functional blocks and the block internal wiring, a template corresponding to a clock tree is formed, and the cells and the wires are laid out based on the clock tree structure on the template. Since the delay time can be adjusted, the respective cells of the respective functional blocks in one semiconductor integrated circuit or respective cells of respective semiconductor integrated circuits in one system can be synchronized one another.

Abstract: A verification support system wherein before a CPU mounted circuit is actually made such circuit model and an ICE model are made virtually and verification of such circuit model is performed using logic simulation on the ICE model; and when an error is found execution and verification up to the error point are omitted and are performed immediately after the error point to correct the error. A waveform, obtained by logic simulation, and a partially enlarged waveform thereof are displayed on different display regions for each time period and a display region is provided for saving a displayed waveform obtained when logic simulation is stopped. In another aspect of the invention, before an actual system is made by PLC, such PLC model is verified, and a test program is carried out to obtain verification when a process model is detached from the PLC model, and a sequence program is carried out by using a general purpose simulator with a debugging function.

Abstract: A vibration/noise active control system for automotive vehicles which generates a canceling signal for canceling vibrations and noises generated within the compartment of the vehicle, based on a reference signal related to the vibrations and noises by means of an adaptive filter. The canceling signal is converted into a canceling sound. The adaptive filter has a filter coefficient thereof changed based on the cancellation error between the canceling sound and the vibrations and noises within the compartment, detected by an error sensor, and the reference signal. A memory stores a plurality of filter coefficient values of the adaptive filter corresponding to a plurality of predetermined traveling conditions of the vehicle.

Abstract: A computer implemented method provides for orientation and lay-out asymmetrical semiconductor devices. The sources of operating potential (20, 30) are identified. The PMOS transistors (22-28) are combined between the first (more positive) source of operating potential and a common node (12) into a combination block (48). The NMOS transistors (14-18) are combined between the common node and the second (less positive) source of operating potential into another combination block (52). The PMOS source terminals are coupled to more positive potentials, and the PMOS drain terminals are coupled to less positive potentials within the first combination block. The NMOS source terminals are coupled to less positive potentials, and the NMOS drain terminals are coupled to more positive potentials within the second combination block. For transmission gates (60, 62), a driving source is identified and the PMOS and NMOS source terminals are coupled to the driving source.

Abstract: A method and apparatus are provided for measuring effective focus of an electron beam directed at a target. The electron beam imparts heat flux into the target to effect a target surface temperature profile thereon. A mathematical process model is used to predict an initial iteration of the temperature profile based on operating beam parameters and based on heat transfer behavioral relationships of the target. The temperature profile is optically measured and then compared with the initial iteration to obtain a residual error therebetween. The predicted temperature profile is iterated by varying the beam focus operating parameter until the residual error is less than a predetermined value for determining the effective beam focus.

Abstract: A host data processing system operating under the control of a host operating system such as an enhanced version of the UNIX operating system on a RISC based hardware platform includes an emulator which runs as an application process for executing emulated system (ES) user application programs. The emulator includes a number of emulated system executive service components including a socket command handler unit and a socket library component operating in shared memory and an interpreter, an emulator monitor call unit (EMCU) and a number of server components operating in host memory. The host operating system further includes a host socket library interface layer (API) which operatively connects through a TCP/IP network protocol stack to the communications facilities of the hardware platform. The socket server components operatively connect ES TCP/IP application programs to the socket library interface layer of the host operating system when such application programs issue standard ES socket library calls.

Abstract: Electronic system for calculating injection time in which an electronic unit with microprocessor receives as input a multiplicity of signals measured in the engine and a signal proportional to the engine load, for example a signal generated by a pressure sensor arranged in the intake manifold of the engine. The electronic unit comprises a circuit for compensating for the delay times due to the response inertia of the engine load sensor, the conditioning (filtering, conversion and processing) of the load signal and physical actuation of the injection. The electronic unit also comprises a circuit for the dynamic compensation of the "film/fluid" effect.

Abstract: In order to estimate an initial potential value for semiconductor device simulation at each of iterative procedures a computer system, a plurality of bias conditions are stored in a memory. Following this, one bias condition is retrieved from the memory at a given iterative procedure. Further, an analysis result already obtained in an iterative procedure, which precedes the given iterative procedure, is retrieved from the memory. Subsequently, an initial potential value is estimated which is used in the give iterative procedure by solving a Laplace equation which is weighted by a coefficient including a reciprocal of electric field intensity.

Abstract: A line length extracting means (2) establishes a correspondence between line length data extracted from layout data (D2) and output lines in an LSI circuit specified by LSI circuit connection data (D1), respectively, to output line length data (D5) to a model selecting means (3), which in turn compares the total line length of each output line (output signal) with a predetermined reference line length (SL) on the basis of the line length data (D5) and selects an RC model for the output line having the total line length greater than the reference line length (SL) and a C model for the output line having the total line length less than the reference line length (SL) to output a model selection result (D6) in which selected model names correspond to output signal names to a wiring delay element inserting means (4), whereby a device and method for calculating an accurate delay time at high speeds is provided.