Abstract: A mechanism is provided in a data processing system comprising at least one processor and at least one memory, the at least one memory comprising instructions that are executed by the at least one processor and configure the at least one processor to implement a device context device driver for forced detaching of an application from mapped devices. The device context device driver receives a command to detach an application, wherein the command specifies a process descriptor associated with the application. The device context device driver identifies a plurality of matching device context entries in a list of open device contexts maintained by the device context device driver that match the process descriptor. The device context device driver marks the plurality of matching device context entries as detached. The device context device driver invalidates mapped memory areas associated with the plurality of matching device context entries.

Abstract: An apparatus is provided, where the apparatus includes a plurality of input/output (I/O) ports and a controller. A first port, a second port, and a third port are to be respectively coupled to a first device with a first class type, a second device with a second class type, and a third device with a third class type. The controller is to determine that individual ones of the first and second devices are to perform asynchronous transfer with the apparatus, and that the third device is to perform a transfer that is different from the asynchronous transfer. The controller is to allocate bandwidth to the first and second I/O ports, based at least in part on the first class type and the second class type. The controller is to ignore the third class type, while allocating bandwidth to the third I/O port.

Abstract: A network adaptor (or NIC) is equipped with multi-level protocol processing capability and is implemented with a protocol processing pipeline that has multiple tap points to enable the integration of co-processors to operate with the NIC. The capability leverages the protocol processing pipeline and all the existing NIC software while at the same time enabling the integration of value added co-processors to customize and enhance the NIC capabilities.

Abstract: Techniques and mechanisms for performing in-memory computations with circuitry having a pipeline architecture. In an embodiment, various stages of a pipeline each include a respective input interface and a respective output interface, distinct from said input interface, to couple to different respective circuitry. These stages each further include a respective array of memory cells and circuitry to perform operations based on data stored by said array. A result of one such in-memory computation may be communicated from one pipeline stage to a respective next pipeline stage for use in further in-memory computations. Control circuitry, interconnect circuitry, configuration circuitry or other logic of the pipeline precludes operation of the pipeline as a monolithic, general-purpose memory device. In other embodiments, stages of the pipeline each provide a different respective layer of a neural network.

Abstract: In an example, an apparatus comprises a plurality of execution units, and logic, at least partially including hardware logic, to assemble a general register file (GRF) message and hold the GRF message in storage in a data port until all data for the GRF message is received. Other embodiments are also disclosed and claimed.

Abstract: This provides an optimized multiport NVMe controller on a single die that significantly reduces area and gate count for multipath I/O requirements over prior implementations without compromising any performance requirements. The arrangement implements minimal logic per NVMe controller as per NVMe specification requirements and implements shared logic for all common functions. This results in the desired substantial savings in gate count and area. The optimized multiport NVMe controller is used in multipath I/O-based memory subsystem where multiple hosts access Namespaces through their own dedicated queues. Illustratively, the optimized multiport NVMe controller shares common logic among NVMe controllers, providing area efficient solution for multipath I/O implementations. Shared logic across all NVMe controllers are the DMA Engine (Hardware block which handles all NVMe commands based on PRP or SGL pointers), Firmware Request Queue (FWRQ). Firmware Completion Queue (FWCQ) and DMACQ (DMA Completion Queue).

Abstract: A signature is generated to indicate a direct memory access (DMA) operation involving a transfer, by a DMA engine, of data between a host memory circuit and an endpoint memory circuit of an endpoint processor circuit. First descriptors of the DMA engine are defined relative to the endpoint memory circuit or host memory circuit. A signature is received that indicates that second descriptors have been configured by the endpoint processor circuit. In response to receiving the endpoint signature, the DMA engine is enabled to begin the DMA operation.

Abstract: Embodiments of the present invention provide a connecting apparatus and a system. The connecting apparatus includes N interconnection units, M line processing units, and X switch processing units, where each interconnection unit is connected to at least one switch processing unit, each switch processing unit is connected to only one interconnection unit, each interconnection unit is connected to the M line processing units, each line processing unit is connected to the N interconnection units, M is a positive integer, N is a positive integer, and X is greater than or equal to N. In addition, the embodiments of the present invention further provide another connecting apparatus and system. According to the foregoing technical solutions, a connecting mode between an LPU and an SPU is relatively flexible.

Abstract: According to an embodiment, a computer system includes a main device, a first computer unit and a second computer unit. The main device includes a first accommodation portion and a second accommodation portion. The main device includes a selector switch, a first selector, a second selector and a control circuit. The first selector conducts either one of first signal lines extended from the first accommodation portion or the second accommodation portion. The second selector conducts either one of second signal lines extended from the first accommodation portion or the second accommodation portion. The control circuit controls the first selector and the second selector by the selector switch.

Abstract: A tablet information handling system keyboard stand stores pairing information in non-transitory memory accessed by an embedded controller upon detection of a physical connection with a tablet information handling system and communicated to an embedded controller in the tablet information handling system through the physical interface. Embedded controller cooperation coordinates configuration of a wireless personal area network interface without wireless communication or power applied to the wireless networking resources.

Abstract: A processor scheduling structure, a method and an integrated circuit are provided. In accordance with at least one embodiment, the processor scheduling structure comprises a processor circuit and an operating system task aware caching (OTC) controller circuit coupled to the processor circuit. The OTC controller circuit comprises a load request timer, a load sequence queue (LSQ), and a request arbiter. The timer and the LSQ are coupled to and provide inputs to the request arbiter. The processor circuit comprises an internal memory and a processor core. The OTC controller circuit is configured to schedule processor tasks for the processor circuit in accordance with both priority-based scheduling, using the LSQ, and time-triggered scheduling, using the load request timer.

Abstract: Methods and apparatus for augmenting routing resources. In one exemplary embodiment, a Thunderbolt™ transceiver incorporates a Peripheral Component Interconnect Express (PCIe) bus that supports hot-plugging and hot-unplugging of peripheral devices. Unfortunately, for various backward compatibility reasons, existing PCIe bus enumeration protocols can quickly exhaust the PCIe routing resources (for example, PCIe bus numbers) resulting in undesirable consequences (for example, crashes, dead connections, etc.) The present disclosure describes schemes for augmenting the pool of PCIe bus numbers and dynamically re-assigning PCIe bus numbers, so as to eliminate the aforementioned concerns.

Abstract: A system is configured to use a de-randomizer and budget data structure to economize I/O operations for a shared storage device while still allowing access to the device to a number of different entities. Embodiments can identify a comparatively low cost next operation as compared to other I/O operations, including a cost for seek time, for a first entity to dispatch to the storage device when the first entity has sufficient budget to have the I/O operation performed on its behalf and to identify an I/O operation for a second entity to dispatch to the storage device when there is insufficient budget for the first entity.

Abstract: The present invention provides an all-in-one machine, a method for the all-in-one machine to realize quick touch in all channels, and a computer storage medium. The method includes: detecting which channel is currently connected to the main board, and controlling a USB selecting switch to connect a first data port of a touch frame with a USB port of a device or module to which the currently connected channel belongs, based on the detected channel information; determining whether there is an action to call a touch menu when detecting that the channel connected to the main board is an internal PC module channel or an external device channel; and if so, activating the main board to start a touch menu application program, and making response, by the main board, to touch data within an area of the touch menu transmitted from the touch frame through the second data port, after the touch menu has been called and before an action of leaving the touch menu is detected.

Abstract: A method, system, and computer program product are provided for determining whether a control unit for an attached device has lost knowledge of a supported host enabled facility associated with the attached device. I/O instructions are initiated that include a first instruction to determine whether the control unit currently has knowledge of the host enabled facility and a second instruction providing knowledge of the host enabled facility by the control unit. Based on responses from the control unit to the I/O instructions, it is determined whether the control unit has transitioned from not having knowledge of the host enabled facility to having such access. If it is determined that the control unit has made such transition as a result of the sequence of I/O instructions, parameters for use with the host enabled facility are initialized; otherwise, such initialization is prevented.

Abstract: Embodiments of a bus interface system are disclosed. The bus interface system includes a master bus controller and a slave bus controller coupled to a bus line. The master bus controller and the slave bus controller are configured to perform read operations using error codes and error checks. For example, the error codes may be cyclic redundancy codes (CRC). In this manner, accuracy is ensured during communications between the slave bus controller and the master bus controller.

Abstract: A method is provided. The method includes receiving, at a first device, a request to transfer data over a Management Data Input/Output (MDIO) communication bus. The first device is configured to generate a first Management Data Clock (MDC) signal. The method also includes determining whether a second MDC signal from a second device is present on the communication bus. The method further includes in response to determining that the second MDC signal is not present on the communication bus, transmitting the first MDC signal and at least part of a Management Data Input/Output (MDIO) frame over the communication bus. The method includes in response to determining that the second MDC signal is present on the communication bus, refraining from transmitting the first MDC signal and at least the part of the MDIO frame over the communication bus.

Abstract: Systems, apparatuses, and methods for reducing the toggle rates on buses are disclosed. A computing system includes a source which provides packets for transmission on a bus. The packet is compressed by a compression engine. The compressed data format of the packet includes locations (bit positions) referred to as holes which do not include valid data. A bus configuration module identifies the locations of the holes and replaces the holes with information from a previous packet transmitted earlier on the bus. The bus configuration module also determines a new transmission bus width for the packet for lowering the bus toggle rate on the bus during transmission.

Abstract: A system for sharing input/output using universal sleds includes a first universal sled that includes a first switch and a first universal node, and a second universal sled that includes a second switch and a second universal node, where the first universal sled and second universal sled have interchangeable physical dimensions. The midplane board includes a management processor and a midplane switch. The system further includes an input/output sled and a bus that connects the first universal sled, the second universal sled, the midplane board, and the input/output sled.

Abstract: A method and a device for sharing a PCIe I/O device, and an interconnection system are provided. The method includes: determining a shared PCIe I/O device in a PCIe interconnection system; establishing, by using a BAR at a working node, a first mapping relationship between an address of a CSR of the shared PCIe I/O device and an address, used for processing the CSR, in a working node domain. The method also includes establishing, by using an A-LUT fragment at a management node side of the NTB, a second mapping relationship between an address, used for receiving an MSI-X interrupt of the shared PCIe I/O device, in a management node domain and an address, used for processing the MSI-X interrupt, in the working node domain.