Abstract: A circuit comprising a plurality of groups of memory cells and a control circuit. The plurality of groups of memory cells may each (i) have a first and a second bitline and (ii) configured to read and write data to one or more of the plurality of groups of memory cells. The control circuit may be configured to select an active group of the plurality of groups in response to one or more control signals. The control circuit may be implemented within the groups of memory cells.

Abstract: In a memory device for storing data according to the FIFO principle, an input counter is provided having a value which is modified when data are written into a memory, and having a comparison unit that outputs a status signal concerning presence of data in the memory dependent on a comparison of the counter states. A scanning unit is arranged at the connection between the comparison unit and the input counter. The scanning unit scans the state of the input counter according to a clock signal and outputs the scan result to the comparison unit.