Patents Examined by Hoai Ho
  • Patent number: 8059465
    Abstract: When a voltage level detector detects that a supply voltage reaches a recovery voltage level that requires a recovery operation, a signal generator generates a recovery operation instructing signal for instructing the recovery operation. The recovery operation instructing signal is invalidated if a certain operation mode is executed and validated in other cases.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: November 15, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuaki Isobe, Masatsugu Kojima
  • Patent number: 8050080
    Abstract: Random access memory with CMOS-compatible nonvolatile storage element in series with storage capacitor is described herein. Embodiments may include memory devices and systems that have plurality of row lines, column lines, and memory cells each of which comprising an access transistor, a storage capacitor and a CMOS-compatible non-volatile storage element connected in series. The CMOS-compatible non-volatile storage element may store charges corresponding to a binary value. The node located between the CMOS-compatible non-volatile storage element and the storage capacitor may be defined as a storage node. During read operation, a cell may be selected, and the voltage at the storage node of the cell may be sensed at the corresponding column line, and the binary value may be determined based on at least the sensed voltage.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: November 1, 2011
    Assignee: S. Aqua Semiconductor LLC
    Inventor: G. R. Mohan Rao
  • Patent number: 8050076
    Abstract: According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: November 1, 2011
    Assignee: Broadcom Corporation
    Inventors: Frank Hui, Xiangdong Chen, Wei Xia
  • Patent number: 8036060
    Abstract: In an SDRAM of reduced current consumption, a signal RAS for performing refresh while temporally splitting refresh becomes active N times (where N is an integer and N?2 holds) in a single refresh time period (indicated by a signal REF) to thereby refresh an internal memory array successively. The SDRAM includes a DLL circuit for aligning phase of an internal clock signal with that of an external clock signal that is externally supplied, and a DLL control circuit for exercising control so as to halt operation of the DLL circuit in an interval in which the address signal becomes active one or more times and N?1 times or fewer, this interval being included in an interval in which the signal RAS becomes active N times. The DLL control circuit counts the signal RAS and decodes the value of the count. Operation of the DLL circuit is halted while a prescribed range of count values is being decoded.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: October 11, 2011
    Assignee: Elpida Memory, Inc.
    Inventor: Koichiro Hayashi
  • Patent number: 8036036
    Abstract: A semiconductor device includes at least two adjacent memory cell blocks, each of the memory cell blocks having a plurality of memory cell units, each of memory cell units having a plurality of electrically reprogrammable and erasable memory cells connected in series, a plurality of cell gates for selecting the plurality of memory cells within the two adjacent memory cell blocks, each of the plurality of cell gates being formed with roughly rectangular closed loops or roughly U shaped open loops, each of the loops being connected to a corresponding cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within one of the two adjacent memory cell blocks and being connected to a corresponding memory cell of the memory cells in a corresponding memory cell unit of the plurality of memory cell units within the other memory cell block of the two adjacent memory cell blocks and a plurality of pairs of first and second selection gates for selecting the memory cell block, the
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: October 11, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Nobuyasu Nishiyama
  • Patent number: 8036013
    Abstract: A phase change memory cell may be read by driving a current through the cell higher than its threshold current. A voltage derived from the selected column may be utilized to read a selected bit of a phase change memory. The read window or margin may be improved in some embodiments. A refresh cycle may be included at periodic intervals.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: October 11, 2011
    Assignee: Ovonyx, Inc.
    Inventors: Tyler Lowrey, Ward D. Parkinson, George A. Gordon
  • Patent number: 8027203
    Abstract: Provided is a pipe latch circuit of a multi-bit pre-fetch type semiconductor memory device with an advanced structure.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: September 27, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Beom Ju Shin
  • Patent number: 8027198
    Abstract: A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: September 27, 2011
    Assignee: Halo LSI, Inc.
    Inventors: Tomoko Ogura, Seiki Ogura, Nori Ogura
  • Patent number: 8018685
    Abstract: Provided is an HGA with a radiation structure that can effectively get away the heat generated from a light source. The HGA comprises a suspension and a head comprising a slider and a light source unit. The suspension comprises an opening, and the light source unit projects through the opening to the opposite side to the slider in relation to the suspension. Further, the first and second pads are provided on the upper and lower surfaces of the suspension, respectively, the end surface opposite to the source-installation surface of the light source is connected to the first pad by the first connection member, and an electrode of the head part is connected to the second pad by the second connection member. Thus, heat flow paths can be provided from the light source to the opposed-to-medium surface to allow effective radiation of the heat generated from the light source.
    Type: Grant
    Filed: October 16, 2008
    Date of Patent: September 13, 2011
    Assignees: TDK Corporation, SAE Magnetics (H.K.) Ltd.
    Inventors: Koji Shimazawa, Ryuta Murakoshi
  • Patent number: 7200063
    Abstract: As part of anti-fuse circuitry for a memory device, a preferred exemplary embodiment of the current invention provides a direct connection between an anti-fuse and a contact pad used to provide voltage to that anti-fuse. The contact pad also serves as a voltage source for at least one other part of the memory device. At least one circuit coupled to the anti-fuse is temporarily isolated from it in the event that a voltage present at the pad would damage the circuit or cause the circuit to improperly read the status of the anti-fuse. The contact pad is available during a probe stage of the in-process memory device, but once the device is packaged, access to that contact pad is prevented. At the back end of the production process, the anti-fuse may be accessed through a second pad, whose electrical communication with the anti-fuse is regulated.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: April 3, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Timothy B. Cowles
  • Patent number: 7184329
    Abstract: Circuits and methods are provided for aligning data read from a memory with an output clock signal when the memory is operated at very high clock frequencies. To align data and clock signals when needed, delay is added to the output clock signal during the read operation. This alignment allows various timing specifications to be met when they would otherwise be violated, therefore improving data integrity in the system.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: February 27, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Paul A Silvestri
  • Patent number: 7061059
    Abstract: The invention relates to a high-voltage deep depletion transistor, provided in a semiconductor body (1) having a substrate (2) of a first conductivity type, for example the p-type, and a surface layer (3) of the opposite conductivity type, for example the n-type for an n-channel transistor. To prevent formation of inversion layers below the gate, the channel is subdivided into a plurality of sub-channel regions (7a, 7b, 7c, 7c) mutually separated by p-type regions (11a, 11b, 11c, 11d) which serve to remove generated holes. The p-type regions extend across the whole thickness of the channel and are contacted via the substrate. Each sub-channel region may be subdivided further by intermediate p-type regions (13) to improve the removal of holes.
    Type: Grant
    Filed: December 18, 2000
    Date of Patent: June 13, 2006
    Assignee: Koninklijke Philips Electronics, N.V.
    Inventors: Constantinus Paulus Meeuwsen, Adrianus Willem Ludikhuize
  • Patent number: 7057925
    Abstract: In read operation, a current from a current supply transistor flows through a selected memory cell and a data line. Moreover, a bias magnetic field having such a level that does not destroy storage data is applied to the selected memory cell. By application of the bias magnetic field, an electric resistance of the selected memory cell changes in the positive or negative direction depending on the storage data level. A sense amplifier amplifies the difference between voltages on the data line before and after the change in electric resistance of the selected memory cell. Data is thus read from the selected memory cell by merely accessing the selected memory cell. Moreover, since the data line and the sense amplifier are insulated from each other by a capacitor, the sense amplifier can be operated in an optimal input voltage range regardless of magnetization characteristics of the memory cells.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: June 6, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Tsukasa Ooishi, Hideto Hidaka
  • Patent number: 7046559
    Abstract: There is disclosed a semiconductor memory device including a memory cell array containing a plurality of banks each having one or more blocks, a data erase circuit configured to erase data from selected blocks in banks at a unit of block, and an automatic multi-block erase circuit configured to enable a data read circuit configured to read data from memory cells provided in one bank, when data erase operation for all erase-object blocks in the one bank is completed, while continuing a data erasing operation of a next erase-object block included in another bank.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: May 16, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hidetoshi Saito
  • Patent number: 7035148
    Abstract: An output driver effectively controls the slew rate of an output signal according to CAS latency information including frequency information of an operating clock signal or according to frequency information obtained by detecting the frequency of the operating clock signal. The output driver includes an output terminal, a pull-up driver which pulls-up the output terminal, and a pull-down driver which pulls-down the output terminal. Also, the output driver further includes a mode register set (MRS) which stores CAS latency information of the semiconductor memory device. Driving capabilities of the pull-up driver and the pull-down driver are varied in response to the CAS latency information. The output driver may include a frequency detector which detects and stores the operating frequency of the semiconductor memory device. In this case, the driving capabilities of the pull-up driver and the pull-down driver are varied in response to output signals output from the frequency detector.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: April 25, 2006
    Assignee: Samusng Electronics Co., Ltd.
    Inventors: Hoe-ju Chung, Kyu-hyoun Kim
  • Patent number: 7031198
    Abstract: In a non-volatile semiconductor memory device of the present invention, in the case of reading information from a second non-volatile memory element of an (i)-th twin memory cell and from a first non-volatile memory element of an (i+1)-th twin memory cell in the row direction, where i is an integer of not less than 1, the process senses an (i?1)-th bit line connecting with a first non-volatile memory element of the (i)-th twin memory cell, so as to detect an electric current running between the (i?1)-th bit line and an (i)-th bit line connecting with the second non-volatile memory element of the (i)-th twin memory cell, via the second non-volatile memory element of the (i)-th twin memory cell.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: April 18, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Masahiro Kanai
  • Patent number: 7031187
    Abstract: To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages are applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information.
    Type: Grant
    Filed: April 27, 2004
    Date of Patent: April 18, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Yusuke Jyouno, Takayuki Kawahara, Katsutaka Kimura
  • Patent number: 7020027
    Abstract: A method of programming a nonvolatile memory cell in which a ramped control voltage is used to obtain the desired voltage on the storage node.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: March 28, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Pavel Poplevine, Yuri Mirgorodski, Andrew J. Franklin, Peter J. Hopper
  • Patent number: 7012843
    Abstract: A device for driving a memory cell (601) of a memory module which can be operated with an external voltage (VEXT) and an operating frequency (fCLK), whereas the memory cell (601) has a capacitance (600) for storing charges and a transistor (602) for reading charges from the capacitance (600) and for writing charges to the capacitance (600), which transistor can be controlled with a control voltage (VPP), which has a charge store (614) for supplying a control voltage (VPP) which is greater than the external voltage (VEXT). The charge store (614) being able to be charged by the external voltage (VEXT), and the charging of the charge store (614) is able to be controlled by a charging control frequency (fCC) derived from the operating frequency (fCLK) of the memory module.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: March 14, 2006
    Assignee: Infineon Technologies AG
    Inventors: Peter Schroegmeier, Thilo Marx, Manfred Dobler
  • Patent number: RE39227
    Abstract: A content addressable memory (CAM) cell that includes a static random access memory (SRAM) cell that operates in response to a VCC supply voltage. A first set of bit lines coupled to the SRAM cell are used to transfer data values to and from the SRAM cell. The signals transmitted on the first set of bit lines have a signal swing equal to the VCC supply voltage. A second set of bit lines is coupled to receive a comparison data value. The signals transmitted on the second set of bit lines have a signal swing that is less than the VCC supply voltage. For example, the signal swing on the second set of bit lines can be as low as two transistor threshold voltages. The second set of bit lines is biased with a supply voltage that is less than the VCC supply voltage. A sensor circuit is provided for comparing the data value stored in the CAM cell with the comparison data value. The sensor circuit pre-charges a match scan line prior to a compare operation.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: August 8, 2006
    Assignee: Integrated Device Technology, Inc.
    Inventors: Chuen-Der Lien, Chau-Chin Wu