Patents Examined by Hoai V. Ho
  • Patent number: 12217782
    Abstract: The disclosed MTJ read circuits include a current steering element coupled to the read path. At a first node of the current steering element, a proportionally larger current is maintained to meet the requirements of a reliable voltage or current sensing. At a second node of the current steering element, a proportionally smaller current is maintained, which passes through the MTJ structure. The current at the first node is proportional to the current at the second node such that sensing the current at the first node infers the current at the second node, which is affected by the MTJ resistance value.
    Type: Grant
    Filed: June 9, 2023
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gaurav Gupta, Zhiqiang Wu, Yih Wang
  • Patent number: 12211543
    Abstract: Mitigating or managing an effect known as “rowhammer” upon a DRAM device may include a memory controller receiving an activation count threshold value from the DRAM device. The memory controller may detect row activation commands directed to the DRAM device and count the number of the row activation commands. The memory controller may send a mitigative refresh command to the DRAM device based on the result of comparing the counted number of row activation commands with the received activation count threshold value.
    Type: Grant
    Filed: September 8, 2022
    Date of Patent: January 28, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Victor Van Der Veen, Pankaj Deshmukh, Behnam Dashtipour, David Hartley
  • Patent number: 12211586
    Abstract: A device includes a first memory subarray, a first modulation circuit, a second memory subarray, a second modulation circuit and a control signal generator. The first modulation circuit is coupled to the first memory subarray. The second memory subarray is located between the first memory subarray and the first modulation circuit along a direction. The second modulation circuit is coupled to the second memory subarray. The control signal generator is configured to generate a first control signal to trigger the first modulation circuit according to a first length of the first memory subarray along the direction, and configured to generate a second control signal to trigger the second modulation circuit according to a second length of the second memory subarray along the direction.
    Type: Grant
    Filed: September 27, 2023
    Date of Patent: January 28, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITED
    Inventors: Xiu-Li Yang, He-Zhou Wan, Mu-Yang Ye, Lu-Ping Kong, Ming-Hung Chang
  • Patent number: 12211542
    Abstract: Embodiments provide a control circuit and a dynamic random access memory. A first connector of the memory chip connects to an input terminal of a functional circuit via a first switch circuit, and an output terminal of the functional circuit connects to a second connector via a second switch circuit, where the first switch circuit and the second switch circuit correspond to a first switch state. A second connector is connected to an input terminal of a functional circuit via a third switch circuit, and an output terminal of the functional circuit is connected to the first connector via a fourth switch circuit, where the third switch circuit and the fourth switch circuit correspond to a second switch state. The switch circuit can control the first switch state or second switch state to be an on state on a basis of a location parity signal of the memory chip.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: January 28, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Jiarui Zhang
  • Patent number: 12205629
    Abstract: A memory device includes pages each constituted by memory cells on a substrate. Voltages applied to first and second gate conductor layers and impurity layers in each memory cell are controlled to retain positive holes inside a channel semiconductor layer. In a page write operation, the voltage of the channel semiconductor layer is set to a first data retention voltage. In a page erase operation, the applied voltages are controlled to discharge the positive holes, and the voltage of the channel semiconductor layer is set to a second data retention voltage. At a second time after a first time, a memory re-erase operation is performed for the channel semiconductor layers at the second data retention voltage at the first time. At a third time after the second time, a memory re-write operation is performed for the channel semiconductor layers at the first data retention voltage at the first time.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: January 21, 2025
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Koji Sakui, Nozomu Harada
  • Patent number: 12205631
    Abstract: A random access memory, including a write transistor with a gate electrically connected to a write word line and a drain electrically connected to a write bit line, a first read transistor and a second read transistor with gates electrically connected to a source of the write transistor to form a storage node, drains electrically connected to a read bit line and a common source electrically connected to a read word line so that the first read transistor and a second read transistor are in parallel connection, and a capacitor electrically connected to the storage node.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: January 21, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Hsiu Wu, Tsung-Hsun Wu
  • Patent number: 12198753
    Abstract: A memory device includes a peripheral circuit structure and a cell array structure vertically overlapping the peripheral circuit structure. The cell array structure includes a plurality of memory blocks divided into a normal cell region and a dummy cell region, and the dummy cell region includes a bit line through-electrode region. The peripheral circuit structure includes a row decoder region in which a unit row decoder circuit connected to each of n (n is a positive integer) memory blocks is arranged, and the bit line through-electrode region is disposed to correspond to the block height of the unit row decoder circuit.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: January 14, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seungyeon Kim, Jooyong Park, Hongsoo Jeon
  • Patent number: 12198770
    Abstract: A memory device, such as a 3D AND flash memory, includes a memory cell block, a word line driver, and a plurality of bit line switches. The word line driver has a plurality of complementary transistor pairs for respectively generating a plurality of word line signals for a plurality of word lines. Substrates of a first transistor and a second transistor of each of the complementary transistor pairs respectively receive a first voltage and a second voltage. Each of the bit line switches includes a third transistor. A substrate of the third transistor receives a third voltage. The first voltage, the second voltage, and the third voltage are constant static voltages during a soft program operation and a soft program verify operation.
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: January 14, 2025
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Teng-Hao Yeh, Hang-Ting Lue, Tzu-Hsuan Hsu, Chen-Huan Chen, Ken-Hui Chen
  • Patent number: 12198768
    Abstract: A semiconductor device and an erasing method may control a number of times an erase pulse. The erasing method of a flash memory includes the following. Multiple sacrificial memory cells in a block are programmed with different write levels first. When a selected block is erased in response to an erase command, a monitor erase pulse (R1) is applied to a well, and then the sacrificial memory cells are verified (S_EV). When the verification fails, a voltage of the monitor erase pulse is increased and then a monitor erase pulse (R2) is applied until the verification of the sacrificial memory cells passes. When the verification is passed, a normal erase pulse (Q1) is applied to the well based on a voltage of the monitor erase pulse (R2) to erase the selected block.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: January 14, 2025
    Assignee: Winbond Electronics Corp.
    Inventor: Masaru Yano
  • Patent number: 12190989
    Abstract: A data output buffer includes a first driver configured to drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to an impedance calibration code and a second driver configured to perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to the impedance calibration code.
    Type: Grant
    Filed: June 13, 2023
    Date of Patent: January 7, 2025
    Assignee: SK hynix Inc.
    Inventors: Kyu Dong Hwang, Bo Ram Kim, Dae Han Kwon
  • Patent number: 12190990
    Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.
    Type: Grant
    Filed: September 26, 2023
    Date of Patent: January 7, 2025
    Assignee: Rambus Inc.
    Inventors: James E. Harris, Thomas Vogelsang, Frederick A. Ware, Ian P. Shaeffer
  • Patent number: 12190969
    Abstract: A memory apparatus and operating method are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes and configured to retain a threshold voltage. The memory holes are organized in rows grouped in strings and the strings comprise a plurality of blocks which comprise planes. A control means is configured to program the memory cells connected to one of the word lines and associated with one of the strings in each of the plurality of planes and acquire a smart verify programming voltage individually for each of the planes in a smart verify operation. The control means concurrently programs at least some of the memory cells connected to each of the word lines in each of the planes in a program operation using the smart verify programming voltage individually acquired for each of the planes in the smart verify operation.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: January 7, 2025
    Assignee: SanDisk Technologies LLC
    Inventors: Ke Zhang, Liang Li
  • Patent number: 12190928
    Abstract: A magnetoresistive random access memory device includes a pinned layer; a tunnel barrier layer on the pinned layer; a free layer structure on the tunnel barrier layer, the free layer structure including a plurality of magnetic layers and a plurality of metal insertion layers between the magnetic layers; and an upper oxide layer on the free layer structure, wherein each of the metal insertion layers includes a non-magnetic metal material doped with a magnetic material, and the metal insertion layers are spaced apart from each other.
    Type: Grant
    Filed: October 21, 2022
    Date of Patent: January 7, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Younghyun Kim, Sechung Oh, Heeju Shin, Jaehoon Kim, Sanghwan Park, Junghwan Park
  • Patent number: 12190937
    Abstract: A memory device is provided that comprises: a memory cell array having a plurality of memory cells connected between a plurality of word lines and a plurality of column lines; a three-phase word line controller configured to generate a selected operating voltage, a first unselected operating voltage, and a second unselected operating voltage having a lower level than the first unselected operating voltage; and a row decoder connected to the plurality of word lines, configured to apply the selected operating voltage to an activated word line on the basis of a row address, and to apply the first unselected operating voltage or the second unselected operating voltage to a deactivated word line.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: January 7, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Byoung Kon Jo
  • Patent number: 12183402
    Abstract: Disclosed is an operation method of a memory device that includes a memory block including a plurality of cell transistors stacked in a direction perpendicular to a substrate. The plurality of cell transistors may include a ground selection transistor and an erase control transistor. The erase control transistor may be between the substrate and the ground selection transistor. The operation method may include performing a first erase operation on the ground selection transistor, performing a first program operation on the erase control transistor after the first erase operation, performing a second program operation on the ground selection transistor after the first program operation, and performing a second erase operation on the erase control transistor after the second program operation.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: December 31, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-Ho Seo, Yong-Wan Son, Dogyeong Lee, Youngha Choi
  • Patent number: 12183390
    Abstract: Disclosed is a memory device which includes a memory core that includes a plurality of memory cells, and control logic that receives a first active command and a first row address from an external device and activates memory cells corresponding to the first row address from among the plurality of memory cells in response to the first active command. The control logic includes registers and counters. The control logic records the first row address in one of the registers, counts an activation count of the first row address by using a first counter of the counters, and counts a lifetime count of the first row address by using a second counter of the counters.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: December 31, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hijung Kim, Jung Min You, Seong-Jin Cho
  • Patent number: 12182455
    Abstract: Examples herein relate to a solid state drive that includes a media, first circuitry, and second circuitry. In some examples, the first circuitry is to execute one or more commands. In some examples, the second circuitry is to receive a configuration of at one type of command, where the configuration is to define an amount of media bandwidth allocated for the at one type of command; receive a command; and assign the received command to the first circuitry for execution.
    Type: Grant
    Filed: November 14, 2023
    Date of Patent: December 31, 2024
    Assignee: Intel Corporation
    Inventors: Nilesh N. Shah, Chetan Chauhan, Shigeki Tomishima, Nahid Hassan, Andrew Chaang Ling
  • Patent number: 12184285
    Abstract: A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and an enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal. In response to the corresponding disabling logic level of the latched clock signal, the input latch is configured to hold a logic level of the latched output signal unchanged, regardless of the input signal having one or more logic level switchings, while the enable signal is having the disabling logic level.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: December 31, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITED
    Inventors: XiuLi Yang, Kuan Cheng, He-Zhou Wan, Ching-Wei Wu, Wenchao Hao
  • Patent number: 12176032
    Abstract: Different ramp rates for different regions, or zones, of word lines are used for the pass voltage applied to unselected word lines during a program operation. The properties of the word lines, such as their resistance and capacitance (RC) values, vary across the NAND memory array. By determining the RC values of the word lines across the array, the word lines can be broken into multiple zones based on these properties. The zones can then be individually assigned different ramp rates for applying a pass voltage to the unselected word lines, where a parameter for the ramp rates can be stored as a register value on the memory die.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: December 24, 2024
    Assignee: SanDisk Technologies LLC
    Inventors: Abu Naser Zainuddin, Jiahui Yuan, Towhidur Razzak
  • Patent number: 12176022
    Abstract: Disclosed herein are related to a memory device. In one aspect, the memory device includes a memory array including a set of memory cells. In one aspect, each of the set of memory cells includes a corresponding transistor and a corresponding capacitor connected in series between a bit line and a select line. In one aspect, the memory device includes a first transistor including a source/drain electrode coupled to a controller and another source/drain electrode coupled to the bit line. In one aspect, the memory device includes a second transistor including a gate electrode coupled to the bit line. In one aspect, the second transistor is configured to conduct current corresponding to data stored by a memory cell of the set of memory cells.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: December 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Jun Wu, Yun-Feng Kao, Sheng-Chih Lai, Katherine H. Chiang, Chung-Te Lin