Abstract: A memory includes: a plurality of memory banks suitable for storing data; a read peripheral region including circuits suitable for transferring data that are read from one memory bank among the memory banks to a memory controller during a read operation; a write peripheral region including circuits suitable for transferring write data that are transferred from the memory controller to one memory bank among the memory banks during a write operation; and a self-refresh counter circuit suitable for activating a self-refresh read signal for activating the read peripheral region whenever a self-refresh operation is performed N times, where N is an integer equal to or greater than 1.

Abstract: Implementations described herein relate to interrupting a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, that the memory built-in self-test is to be interrupted while the memory built-in self-test is being performed using a test mode. The memory device may be permitted to interrupt the memory built-in self-test while the memory built-in self-test is being performed using the test mode but may not be permitted to interrupt the memory built-in self-test while the memory built-in self-test is being performed using a repair mode. The memory device may interrupt the memory built-in self-test while the memory built-in self-test is being performed using the test mode.

Abstract: A flash memory system may include a flash memory and a circuit for performing operations on the flash memory. The circuit may be configured to obtain a first soft read sample by performing a first read operation on a location of the flash memory with a first reference voltage. The circuit may be configured to determine a second reference voltage based on the first soft read sample. The circuit may be configured to obtain a second soft read sample by performing a second read operation on the location of the flash memory with the second reference voltage. The circuit may be configured to generate soft information based on the first and second soft read samples. The circuit may be configured to decode a result of a third read operation on the location of the flash memory based on the soft information.

Abstract: Methods, systems, and devices for imprint recovery for memory cells are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.

Abstract: A standard potential used for reading is set flexibly according to the state of a storage device. A data memory cell group stores data. A reference memory cell group stores a plurality of reference potentials. A standard potential generating section selects a prescribed number of reference potentials from among the plurality of reference potentials stored in the reference memory cell group and generates the standard potential. A reference potential selection control section controls the selection by the standard potential generating section according to prescribed conditions. A sense amplifier amplifies data read out from the data memory cell group, by using the standard potential as a standard.

Abstract: The present technology includes a controller controlling an operation of a semiconductor memory device in response to a test request received from an external device. The controller includes a memory test controller and a performance information storage. The memory test controller generates a command corresponding to a test request received from the external device. The performance information storage stores a test operation result of the semiconductor memory device performed in response to the command.

Abstract: A memory device includes a current source and a memory array. The current source is configured to provide a current to a first node. The memory array is coupled to the current source at the first node. The memory array includes memory cells. First terminals of the memory cells are coupled to the first node. Each of the memory cells has a first resistance in response to having a first data value, and has a second resistance in response to having a second data value. The second data value is N times the first data value. The second resistance is approximately one-Nth of the first resistance, for N being a positive integer larger than one. A method of operating a memory device is also disclosed herein.

Abstract: The present disclosure is directed to arranging user data memory cells and test memory cells in a configurable memory array that can perform both differential and single ended read operations during memory start-up and normal memory use, respectively. Different arrangements of the user data memory cells and the test memory cells in the memory array result in increased effectiveness of memory array, in terms of area optimization, memory read accuracy and encryption for data security.

Abstract: A column select signal cell circuit, a bit line sense circuit and a memory are disclosed. The column select signal cell circuit includes four column select cells, each of which includes 4*N input and output ports, 4*N bit line connection ports and one control port. The control ports of a first column select cell and a fourth column select cell are connected to a first column select signal, and the control ports of a second column select cell and a third column select cell are connected to a second column select signal. The bit line connection ports of the first column select cell and the third column select cell are connected to 8*N bit lines of a first storage unit group, the bit line connection ports of the second column select cell and the fourth column select cell are connected to 8*N bit lines of a second storage unit group.

Abstract: A method for accessing of memory cells where a set of user data is stored in a plurality of memory cells of the memory array, including: latching a current row address of a selected plurality of memory access; comparing a last row address with the current row address; if the result of the comparison is negative, executing a leakage compensation algorithm through a memory sensing circuitry; if the result of the comparison is positive, waiting for the completion of a write to read procedure on the selected plurality of memory cells.

Abstract: A memory device includes: a memory cell array; a sense amplifier for amplifying data stored in the memory cell array; a first memory cell sub-array included in the memory cell array directly coupled to the sense amplifier; a switch coupled to the first memory cell sub-array; and a second memory cell sub-array included in the memory cell array coupled to the sense amplifier through the first memory cell sub-array and the switch. When the switch is enabled, the first memory cell sub-array has a first operation speed, and the second memory cell sub-array has a second operation speed slower than the first operation speed. When the switch is disabled, a bit line loading associated with the second memory cell sub-array is decreased, and the first memory cell sub-array has a third operation speed faster than the first operation speed.

Abstract: A memory with reduced power consumption during a write assist period is provided that includes a series of inverters configured to delay a write assist signal to form a delayed write assist signal at a first terminal of a boost capacitor. A cutoff switch transistor couples between ground and a ground node of a final inverter in the series of inverters. A clock circuit switches off the cutoff switch transistor to isolate the first terminal of the boost capacitor before an end of a write assist period.

Abstract: A memory system includes a plurality of memory devices and a controller. Each of the memory devices includes a memory cell array, a sense amplifier for amplifying data stored in the memory cell array, a first memory cell sub-array included in the memory cell array directly coupled to the sense amplifier, a switch coupled to the first memory cell sub-array, and a second memory cell sub-array included in the memory cell array coupled to the sense amplifier through the first memory cell sub-array and the switch. When the switch is enabled, the memory device operates as a normal mode, and when the switch is disabled, the memory device operates as a fast mode faster than the normal mode. The controller dynamically sets a mode of each of the memory devices based on requests externally provided, by controlling the switch of each of the memory devices.

Abstract: A semiconductor memory device includes a plurality of semiconductor patterns extending in a first horizontal direction and separated from each other in a second horizontal direction and a vertical direction, each semiconductor pattern including a first source/drain area, a channel area, and a second source/drain area arranged in the first horizontal direction; a plurality of gate insulating layers covering upper surfaces or side surfaces of the channel areas; a plurality of word lines on the upper surfaces or the side surfaces of the channel areas; and a plurality of resistive switch units respectively connected to first sidewalls of the semiconductor patterns, extending in the first horizontal direction, and separated from each other in the second horizontal direction and the vertical direction, each resistive switch unit including a first electrode, a second electrode, and a resistive switch material layer between the first and second electrodes and including carbon nanotubes.

Abstract: A storage controller for writing first data to a first memory cell by performing programming of the first memory cell N-times, where N is a positive integer greater than 1, includes a write amplification manager and a central processing unit. The write amplification manager checks whether the first data is invalid data before an Nth programming of the first memory cell is performed, and the central processing unit does not perform the N-th programming of the first memory cell when the first data is the invalid data.

Abstract: A memory array that includes a plurality of storage cells, a plurality of bit lines, a plurality of memory transistor word lines and a plurality of selection transistor word lines, wherein the storage cells form an array of M rows*N columns; each storage cell includes a selection transistor and a memory transistor connected in series; a source and a gate of each selection transistor are connected, and the gates of the selection transistors in the same row are connected to a corresponding selection transistor word line.

Abstract: A method of storing an input data of a data set into a memory storage having bit cells. The method includes determining a bit value of a characterization bit in the input data. The method also includes writing each of remaining bits in the input data into one of the bit cells as a first state if the characterization bit has a first value, and writing each of remaining bits in the input data into the bit cells as a second state if the characterization bit has a second value that is complement to the first value. In the method, either reading the bit cell with the first state consumes less energy than reading the bit cell with the second state or the bit cell with the first state has less retention errors than the bit cell with the second state.

Abstract: A device includes a first memory bank and a second memory bank. The first memory bank is configured to operate according to a write data signal and a first global write signal associated with a first clock signal. The second memory bank is configured to operate according to the write data signal and a second global write signal associated with a second clock signal. One of the first clock signal and the second clock signal is in oscillation when another one of the first clock signal and the second clock signal is in suspension.

Abstract: A semiconductor memory device includes a memory cell array, a page buffer, and control logic. The memory cell array includes a plurality of memory cells for storing data. The page buffer is coupled to at least one memory cell among the plurality of memory cells through a bit line and is configured to store data in the at least one memory cell. The control logic is configured to control an operation of the page buffer. The page buffer includes a first transistor coupled between the bit line and a first node, a second transistor coupled between the bit line and an external power voltage terminal, and an internal operation circuit coupled to the first node.

Abstract: A semiconductor device in which energy required for data transfer between an arithmetic device and a memory is reduced is provided. The semiconductor device includes a peripheral circuit and a memory cell array. The peripheral circuit has a function of a driver circuit and a control circuit for the memory cell array, and an arithmetic function. The peripheral circuit includes a sense amplifier circuit and an arithmetic circuit, and the memory cell array includes a memory cell and a bit line. The sense amplifier circuit has a function of determining whether the bit line is at a high level or a low level, and outputs the result to the arithmetic circuit. The arithmetic circuit has a function of performing a product-sum operation, the result of which is output from the semiconductor device.