Patents Examined by Hoai V. Ho
  • Patent number: 11915789
    Abstract: Systems and methods are provided for controlling a sleep operation for a memory array. A memory system may include a memory array with a memory cell and a word line driver, the memory array receiving a word line clock signal that enables and disables memory read and write operations of the memory cell. The memory array may further including a switching circuit coupled between the word line driver and a power source, the switching circuit being controlled by a local word line sleep signal to turn power to the word line driver on and off. A latch circuit may generate the local word line sleep signal in response to a delayed clock signal and one or more power management control signals. The word line clock signal and the delayed clock signal may both being generated as a function of a memory clock signal.
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Sanjeev Kumar Jain
  • Patent number: 11915759
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: February 27, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Masanobu Shirakawa, Marie Takada, Tsukasa Tokutomi, Yoshihisa Kojima, Kiichi Tachi
  • Patent number: 11915754
    Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Der Chih, Chung-Cheng Chou, Wen-Ting Chu
  • Patent number: 11915778
    Abstract: A semiconductor memory device includes: a core unit including first and second memory cell groups; and a control circuit. The control circuit is configured to, in response to a read command including designation of a first address and designation of a second address, read first data from the first memory cell group, read second data from the second memory cell group, and output third data and fourth data in parallel. The first and second addresses correspond to the first and second memory cell groups, respectively. The designation of the second address is made after the designation of the first address. The third data corresponds to the read first data. The fourth data corresponds to the read second data.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: February 27, 2024
    Assignee: Kioxia Corporation
    Inventors: Daisuke Arizono, Akio Sugahara, Mitsuhiro Abe, Mitsuaki Honma
  • Patent number: 11908543
    Abstract: The present technology may include a first detection unit configured to generate an output signal by detecting a level of an input terminal in response to a transition of a control clock signal during a normal read operation, and a second detection unit configured to generate the output signal by detecting the level of the input terminal regardless of the transition of the control clock signal during a state information read operation.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: February 20, 2024
    Assignee: SK hynix Inc.
    Inventors: Eun Ji Choi, Keun Seon Ahn, Kwan Su Shon, Yo Han Jeong
  • Patent number: 11901032
    Abstract: A memory system includes a memory device and a memory controller. The memory device includes a memory cell array including normal memory cells and redundancy memory cells suitable for replacing failed memory cell among the normal memory cells, and a device controller for activating reserved memory cells which are included in the redundancy memory cells and not used to replace the failed memory cell. The memory controller controls the memory device, when a first memory cells are accessed more than a threshold access number, to move data stored in the first memory cells to the reserved memory cells and replace the first memory cells with the reserved memory cells.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: February 13, 2024
    Assignee: SK hynix Inc.
    Inventors: Hyung-Sik Won, Hyungsup Kim
  • Patent number: 11901039
    Abstract: Apparatuses and techniques for operating devices with multiple differential write clock signals having different phases are described. For example, a memory controller (e.g., of a host device) can provide two differential write clock signals to a memory device over an interconnect. The two differential write clock signals may have a phase offset of approximately ninety degrees. Instead of generating its own phase-delayed write clock signals using a component (e.g., a clock divider circuit) that can enter the metastable state, the memory device can use the multiple differential write clocks signals provided by the memory controller to process memory requests.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: February 13, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Keun Soo Song
  • Patent number: 11894055
    Abstract: A semiconductor device includes: a peripheral circuit region including circuit elements on a substrate, the circuit elements of a page buffer and a row decoder; and a cell region including gate electrode layers, stacked in a first direction, perpendicular to an upper surface of the substrate, and connected to the row decoder, and channel structures extending in the first direction to penetrate through the gate electrode layers and to be connected to the page buffer. The row decoder includes high-voltage elements, operating at a first power supply voltage, and low-voltage elements operating at a second power supply voltage, lower than the first power supply voltage. Among the high-voltage elements, at least one first high-voltage device is in a first well region doped with impurities having a first conductivity-type.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: February 6, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ansoo Park, Ahreum Kim, Homoon Shin
  • Patent number: 11894069
    Abstract: A memory device includes unselected sub-block, which includes bit line; drain select (SGD) transistor coupled with bit line; a source voltage line; source select (SGS) transistor coupled with source voltage; and wordlines coupled with gates of string of cells, which have channel coupled between the SGS/SGD transistors. Control logic coupled with unselected sub-block is to: cause the SGD/SGS transistors to turn on while ramping the wordlines from a ground voltage to a pass voltage associated with unselected wordlines in preparation for read operation; cause, while ramping the wordlines, the channel to be pre-charged by ramping voltages on the bit line and the source voltage line to a target voltage that is greater than a source read voltage level; and in response to wordlines reaching the pass voltage, causing the SGD and SGS transistors to be turned off, to leave the channel pre-charged to the target voltage during the read operation.
    Type: Grant
    Filed: February 2, 2022
    Date of Patent: February 6, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Xiangyu Yang, Hong-Yan Chen, Ching-Huang Lu
  • Patent number: 11894096
    Abstract: A memory system includes a memory device and a memory controller. The memory device includes a memory area configured to store data and an input/output (I/O) buffering part configured to store data outputted from the memory area. The memory controller is configured to control read operations of the memory device. The memory device is configured to store data of all columns in a selected row designated by a row address among a plurality of rows in the memory area into the I/O buffering part in response to an external command outputted from the memory controller and is configured to output data of a selected column designated by a column address among the data stored in the I/O buffering part, and the memory controller is configured to perform a scheduling operation for successively executing read request commands having the same row address among a plurality of read request commands for performing read operations of the memory device.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: February 6, 2024
    Assignee: SK hynix Inc.
    Inventor: Choung Ki Song
  • Patent number: 11894075
    Abstract: A method of cache programming of a NAND flash memory in a triple-level-cell (TLC) mode is provided. The method includes discarding an upper page of a first programming data from a first set of data latches in a plurality of page buffers when a first group of logic states are programmed and verified. The plurality of page buffers include the first, second and third sets of data latches, configured to store the upper page, middle page and lower page of programming data, respectively. The method also includes uploading a lower page of second programming data to a set of cache latches, transferring the lower page of the second programming data from the set of cache latches to the third set of data latches after discarding the lower page of the first programming data, and uploading a middle page of the second programming data to the set of cache latches.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: February 6, 2024
    Assignee: Yangtze Memory Technologies Co. Ltd.
    Inventor: Jason Guo
  • Patent number: 11887645
    Abstract: Dual-precision analog memory cells and arrays are provided. In some embodiments, a memory cell, comprises a non-volatile memory element having an input terminal and at least one output terminal; and a volatile memory element having a plurality of input terminals and an output terminal, wherein the output terminal of the volatile memory element is coupled to the input terminal of the non-volatile memory element, and wherein the volatile memory element comprises: a first transistor coupled between a first supply and a common node, and a second transistor coupled between a second supply and the common node; wherein the common node is coupled to the output terminal of the volatile memory element; and wherein gates of the first and second transistors are coupled to respective ones of the plurality of input terminals of the volatile memory element.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: January 30, 2024
    Assignee: Hefei Reliance Memory Limited
    Inventors: Zhichao Lu, Liang Zhao
  • Patent number: 11881250
    Abstract: Circuits, systems, and methods are described herein for generating a boost voltage for a write operation of a memory cell. In one embodiment, a boost circuit includes a first inverter and a second inverter, each configured to invert a write signal. The boost circuit also includes a transistor and a capacitor. The transistor is coupled to an output of the first inverter. The transistor is configured to charge a capacitor based on the write signal and provide a supply voltage to a write driver. The capacitor is coupled to an output of the second inverter. The capacitor is configured to generate and provide a delta voltage to the write driver.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: January 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Sanjeev Kumar Jain
  • Patent number: 11875831
    Abstract: A controller of a non-volatile memory detects errors in data read from a particular physical page of the non-volatile memory. Based on detecting the errors, the controller performs a read voltage threshold calibration for a page group including the particular physical page and a multiple other physical pages. Performing the read voltage threshold calibration includes calibrating read voltage thresholds based on only the particular physical page of the page group. After the controller performs the read voltage threshold calibration, the controller optionally validates the calibration. Validating the calibration includes determining whether bit error rates diverge within the page group and, if so, mitigating the divergence. Mitigating the divergence includes relocating data from the page group to another block of the non-volatile memory.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: January 16, 2024
    Assignee: International Business Machines Corporation
    Inventors: Roman Alexander Pletka, Radu Ioan Stoica, Nikolas Ioannou, Nikolaos Papandreou, Charalampos Pozidis, Timothy J. Fisher, Aaron Daniel Fry
  • Patent number: 11875860
    Abstract: The present disclosure relates to a non-volatile memory device and to a method for generating overvoltage values in such a memory device structured in a plurality of sub-arrays and including at least a decoding and sensing circuitry associated with each sub-array, a charge pump architecture for each sub-array including pump stages for increasing the value of an input voltage and obtaining an overvoltage output value, a control and JTAG interface in the memory device, and at least a registers block coupled to the charge pump architecture and driven by a logic circuit portion for receiving at least an activation signal selecting a specific charge pump architecture associated with a memory sub-array of the plurality of sub-arrays.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: January 16, 2024
    Inventors: Alberto Troia, Antonino Mondello
  • Patent number: 11869628
    Abstract: An exemplary memory is configurable to operate in a low latency mode through use of a low latency register circuit to execute a read or write command, rather performing a memory array access to execute the read or write command. A control circuit determines whether an access command should be performed using the low latency mode of operation (e.g., first mode of operation) or a normal mode of operation (e.g., second mode of operation). In some examples, a processor unit directs the memory to execute an access command using the low latency mode of operation via one or more bits (e.g., a low latency enable bit) included in the command and address information.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: January 9, 2024
    Inventors: Yuan He, Daigo Toyama
  • Patent number: 11869592
    Abstract: Apparatuses and methods for decoding addresses for memory are disclosed. An example apparatus includes a memory cell array and a row decoder. The memory cell array includes a bank of memory including a plurality of groups of memory. Each of the groups of memory includes sections of memory, and each of the sections of memory including memory cells arranged in rows and columns of memory. The row decoder decodes addresses to access a first group of memory to include rows of prime memory from a first block of memory and to include rows of prime memory from a second block of memory. The row decoder decodes the addresses to access a second group of memory to include rows of prime memory from the second block of memory and to include rows of redundant memory. The rows of redundant memory are shared with the first and second blocks of memory.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: January 9, 2024
    Inventors: Gary L. Howe, Scott E. Smith
  • Patent number: 11869607
    Abstract: Various embodiments enable age tracking of one or more physical memory locations (e.g., physical blocks) of a memory die, which can be from part of a memory device. In particular, various embodiments provide age tracking of one or more physical memory locations of a memory die (e.g., memory integrated circuit (IC)) using one or more aging bins on the memory die, where each aging bin is associated with a different set of physical memory locations of the memory die. By use of an aging bin for a set of physical memory locations, various embodiments can enable a processing device that interacts with a memory die, after the memory die has been subjected to one or more reflow soldering processes, to determine how much the set of physical memory locations have aged after the one or more reflow soldering processes.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: January 9, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Falgun G. Trivedi
  • Patent number: 11862257
    Abstract: A programming pulse is caused to be applied to a wordline associated with a memory cell of the memory sub-system. A program verify operation is caused to be performed on the memory cell to determine that a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sensing node associated with the memory cell. A bitline voltage matching the measured threshold voltage is caused to be applied to a bitline associated with the memory cell to reduce a rate of programming associated with the memory cell.
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: January 2, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Jun Xu, Violante Moschiano, Erwin E. Yu
  • Patent number: 11862259
    Abstract: An electronic device, and an over-erase detection and elimination method for memory cells are provided; the method includes: performing an erase operation on a specified area; selecting all the memory cells in the selected area one by one; measuring a threshold voltage of a selected memory cell for over-erase detection to see if it is less than a normal erase threshold voltage; if not, selecting the next memory cell for over-erase detection, and if yes, then performing a soft-write operation on the selected memory cell; after the soft-write operation, performing over-erase detection again to see whether the threshold voltage of the selected memory cell is within a normal threshold range; and if not, performing a soft-write operation again, and if yes, the next memory cell is selected for over-erase detection, until the threshold voltages of all the memory cells selected for erasure are within the normal threshold range.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: January 2, 2024
    Assignee: CHINA FLASH CO., LTD. SHANGHAI
    Inventors: Hong Nie, Ying Sun