Patents Examined by Hoai V. Ho
  • Patent number: 11190169
    Abstract: A latch circuit includes a latch clock generator configured to generate a latched clock signal based on a clock signal and a first enable signal, and an input latch coupled to the latch clock generator to receive the latched clock signal. The input latch is configured to generate a latched output signal based on the latched clock signal and an input signal. In response to the first enable signal having a disabling logic level, the latch clock generator is configured to set a logic level of the latched clock signal to a corresponding disabling logic level, regardless of the clock signal.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: November 30, 2021
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMIIED
    Inventors: XiuLi Yang, Kuan Cheng, He-Zhou Wan, Ching-Wei Wu, Wenchao Hao
  • Patent number: 11189357
    Abstract: The present application provides a programmable memory device. The programmable memory device includes an active region, a gate structure and an anti-fuse storage unit. The active region is formed in a substrate and having a linear top view shape. The gate structure is disposed on the substrate and having a linear portion intersected with a section of the active region away from end portions of the active region. The anti-fuse storage unit uses a portion of the active region as a terminal, and further comprises an electrode and a dielectric layer. The electrode is disposed on the portion of the active region and spaced apart from the gate structure, and the dielectric layer is sandwiched between the portion of the active region and the electrode.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: November 30, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chin-Ling Huang
  • Patent number: 11189326
    Abstract: A method of cache programming of a NAND flash memory in a triple-level-cell (TLC) mode is provided. The method includes discarding an upper page of a first programming data from a first set of data latches in a plurality of page buffers when a first group of logic states are programmed and verified. The plurality of page buffers include the first, second and third sets of data latches, configured to store the upper page, middle page and lower page of programming data, respectively. The method also includes uploading a lower page of second programming data to a set of cache latches, transferring the lower page of the second programming data from the set of cache latches to the third set of data latches after discarding the lower page of the first programming data, and uploading a middle page of the second programming data to the set of cache latches.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: November 30, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Jason Guo
  • Patent number: 11183251
    Abstract: A non-volatile memory device including: a page buffer configured to latch a plurality of page data constituting one bit page of a plurality of bit pages, and a control logic configured to compare results of a plurality of read operations performed in response to a high-priority read signal set to select one of a plurality of read signals included in the high-priority read signal set as a high-priority read signal, and determine a low-priority read signal corresponding to the high-priority read signal, wherein the high-priority read signal set is for reading high-priority page data, and the low-priority read signal is for reading low-priority page data.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: November 23, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong Jin Shin, Ji Su Kim, Dae Seok Byeon, Ji Sang Lee, Jun Jin Kong, Eun Chu Oh
  • Patent number: 11183227
    Abstract: A magnetic device may include a layer stack. The layer stack may include a first ferromagnetic layer; a spacer layer on the first ferromagnetic layer; a second ferromagnetic layer on the spacer layer; and a dielectric barrier layer on the second ferromagnetic layer. In some examples, the layer stack may also include an additional ferromagnetic layer and an additional spacer layer. The magnetic device also may include a voltage source configured to apply a bias voltage across the layer stack to cause switching of a magnetic orientation of the second ferromagnetic layer without application of an external magnetic field.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: November 23, 2021
    Assignee: Regents of the University of Minnesota
    Inventors: Jian-Ping Wang, Delin Zhang, Protyush Sahu
  • Patent number: 11170859
    Abstract: A memory device, including a plurality of planes, includes a mode setting component to set an operation mode of the memory device as a verify pass mode to allow a verify operation, performed in the plurality of planes, to forcibly pass; and a verify signal generator for outputting a verify pass signal signaling that the verify operation has passed for each of the plurality of planes.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: November 9, 2021
    Assignee: SK hynix Inc.
    Inventors: Tai Kyu Kang, Chul Woo Yang
  • Patent number: 11170825
    Abstract: A data receiving device of a memory device comprises a first pre-amplifier configured to receive previous data, a first reference voltage, and input data, and to output differential signals by comparing the input data with the first reference voltage in response to a clock, when the first pre-amplifier is selected in response to the previous data, a second pre-amplifier configured to receive inverted previous data, a second reference voltage, different from the first reference voltage, and the input data, and outputting a common signal in response to the clock, when the second pre-amplifier is unselected in response to the previous data; and an amplifier configured to receive the differential signals and the common signal, and to latch the input data by amplifying the differential signals.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: November 9, 2021
    Inventors: Jaemin Choi, Daehyun Kwon, Buyeon Lee
  • Patent number: 11164628
    Abstract: An apparatus includes an analog phase change memory array, including an array of cells addressable and accessible through first lines and second lines. The apparatus includes device(s) coupled to one or more of the first lines. The device(s) is/are able to be coupled to or decoupled from the one or more first lines to compensate for phase change memory resistance drift in resistance of at least one of the cells in the one or more first lines. The apparatus may also include control circuitry configured to send, using the first lines and second lines, a same set pulse through the device(s) to multiple individual phase change memory resistors in the phase change memory array sequentially once every period.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ning Li, Wanki Kim, Stephen W. Bedell, Devendra K. Sadana
  • Patent number: 11164889
    Abstract: Some embodiments include a ferroelectric transistor having an active region which includes a first source/drain region, a second source/drain region, and a body region between the first and second source/drain regions. The body region has a different semiconductor composition than at least one of the first and second source/drain regions to enable replenishment of carrier within the body region. An insulative material is along the body region. A ferroelectric material is along the insulative material. A conductive gate material is along the ferroelectric material.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: November 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Durai Vishak Nirmal Ramaswamy, Haitao Liu
  • Patent number: 11164610
    Abstract: A memory device with built-in flexible redundancy is provided according to various aspects of the present disclosure. In certain aspects, a memory device includes a first sense amplifier, a second sense amplifier, a first comparator, a second comparator, a reference circuit, and a logic gate. During a redundant read operation, the first sense amplifier, the first comparator, and the reference circuit are used to read one copy of a redundant bit stored in the memory device, and the second sense amplifier, the second comparator, and the reference circuit are used to read another copy of the redundant bit stored in the memory device. The logic gate may then determine a bit value based on the bit values of the read copies of the redundant bit (e.g., determine a bit value of one if the bit value of at least one of the read copies of the redundant bit is one).
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: November 2, 2021
    Assignee: QUALCOMM INCORPORATED
    Inventors: Anil Chowdary Kota, Hochul Lee
  • Patent number: 11145352
    Abstract: Memory devices and systems with adjustable through-silicon via (TSV) delay, and associated methods, are disclosed herein. In one embodiment, an apparatus includes a plurality of memory dies and a TSV configured to transmit signals to or receive signals from the plurality of memory dies. The apparatus further includes circuitry coupled to the TSV and configured to introduce propagation delay onto signals transmitted to or received from the TSV. In some embodiments, the apparatus includes additional circuitry configured to activate, deactivate, adjust at least a portion of the circuitry, or any combination thereof, to alter the propagation delay. In this manner, the apparatus can align internal timings of memory dies of the plurality of memory dies.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: October 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: John H. Gentry, Michael J. Scott, Greg S. Gatlin, Lael H. Matthews, Anthony M. Geidl, Michael Roth, Markus H. Geiger, Dale H. Hiscock, Evan C. Pearson
  • Patent number: 11145357
    Abstract: A memory system, a memory controller and a method for operating a memory system are disclosed. Specifically, by performing soft-decision decoding for data read from some of the plurality of memory cells based on a first optimum read voltage of one or more optimum read voltages, based on reliability values of one or more first threshold voltage sections, and one or more second threshold voltage sections and also based on the first and second threshold voltage sections, it is possible to provide a memory system, a memory controller and a method for operating a memory system, capable of increasing an error correction effect by soft-decision decoding even in the case where threshold voltage distributions of memory cells in which data is stored are degraded.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: October 12, 2021
    Assignee: SK hynix Inc.
    Inventor: Su-Kyung Kim
  • Patent number: 11145378
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve performance while reading a one-time programmable memory. An example apparatus includes: a voltage boost circuit including a first output, a second output, a first input configured to be coupled to a controller, a second input coupled to a first output of a decoder, a third input coupled to a second output of the decoder; and a multiplexer including a first input coupled to the first output of the voltage boost circuit, a second input coupled to the second output of the voltage boost circuit, a third input coupled to an array of memory, and an output coupled to a sensing circuit.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: October 12, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Suresh Balasubramanian, Stephen Wayne Spriggs, George B Jamison
  • Patent number: 11145360
    Abstract: There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a source layer; a channel structure extending in a first direction from within the source layer; a source-channel contact layer surrounding the channel structure on the source layer; a first select gate layer overlapping with the source-channel contact layer and surrounding the channel structure; a stack including interlayer insulating layers and conductive patterns that are alternately stacked in the first direction and surrounding the channel structure, the stack overlapping with the first select gate layer; and a first insulating pattern that is formed thicker between the first select gate layer and the channel structure than between the stack and the channel structure.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: October 12, 2021
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 11145664
    Abstract: Disclosed is an integrated circuit for ferroelectric memory, the integrated circuit comprising: a ferroelectric memory array having a storage unit array formed on a ferroelectric single-crystal layer, wherein each ferroelectric memory unit in the ferroelectric memory array is at least formed by one storage unit in the storage unit array, or at least formed by one storage unit in the storage unit array and one transistor formed on a silicon substrate of a silicon-based reading and writing circuit that is electrically connected to the storage unit.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: October 12, 2021
    Assignee: Fudan University
    Inventors: Anquan Jiang, Yan Zhang, Zilong Bai
  • Patent number: 11139045
    Abstract: Methods, apparatuses and systems related to managing access to a memory device are described. A memory device includes fuses and latches for storing a repair segment locator and a repair address for each repair of one or more defective memory cells. A segment-address determination circuit generate an active segment address based on the repair address according to the repair segment locator and an address for a read or a write operation. A comparator circuitry is configured to determine whether the active segment address matches the address for the read or the write operation for replacing the one or more defective memory cells with the plurality of redundant cells when the address for the read/write operation corresponds to the one or more defective memory cells.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: October 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Christopher G. Wieduwilt, James S. Rehmeyer, Seth A. Eichmeyer
  • Patent number: 11139301
    Abstract: The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate, a multilayer wiring layer provided over the driver circuit, and a memory cell array layer provided over the multilayer wiring layer. That is, the memory cell array overlaps with the driver circuit. Accordingly, the integration degree of the semiconductor memory device can be increased as compared to the case where a driver circuit and a memory cell array are provided in the same plane of a substrate containing a singe crystal semiconductor material.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: October 5, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuhiko Takemura
  • Patent number: 11133053
    Abstract: Techniques, apparatus, and devices for managing power in a memory die are described. A memory die may include an array of memory cells and one or more voltage sensors. Each voltage sensor may be on the same substrate as the array of memory cells and may sense a voltage at a location associated with the array. The voltage sensors may generate one or more analog voltage signals that may be converted to one or more digital signals on the memory die. In some cases, the analog voltage signals may be converted to digital signals using an oscillator and a counter on the memory die. The digital signal may be provided to a power management integrated circuit (PMIC), which may adjust a voltage supplied to the array based on the digital signal.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: September 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Fuad Badrieh, Thomas H. Kinsley, Baekkyu Choi
  • Patent number: 11133040
    Abstract: A semiconductor memory device includes: a temperature sensor configured to sense an internal temperature of the semiconductor memory device and generate a temperature signal; and a temperature code storage unit configured to receive the temperature signal in response to a temperature code write control signal that is generated when an operation corresponding to a specific command is performed, generate an operating temperature code corresponding to the temperature signal, compare the operating temperature code with a previously stored temperature code, store a larger temperature code of the operating temperature code and the previously stored temperature code as a maximum temperature code, and output the maximum temperature code to an external source in response to a temperature code read control signal.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: September 28, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeonghyeon Cho, Seonghoon Joo, Ilhan Choi
  • Patent number: 11120851
    Abstract: A memory apparatus includes a pseudo static random access memory and a controller. The controller is configured to provide an external command to the pseudo static random access memory. When the memory apparatus starts a burst read operation or a burst write operation, the controller provides a plurality of page starting addresses to the pseudo static random access memory, and the pseudo static random access memory sequentially performs the burst read operation or the burst write operation according to a sequence of receiving the page starting addresses.
    Type: Grant
    Filed: July 12, 2020
    Date of Patent: September 14, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Shinya Fujioka