Abstract: A reference voltage circuit includes a self-decoupling boost circuit coupled between a supply voltage and an output node. The boost circuit provides a boost current to accelerate the transition of the output node's voltage. The boost circuit is controlled by a voltage detection circuit having its input coupled to the output node of the reference voltage circuit. The voltage detection circuit monitors the output voltage of the reference voltage circuit and provides a disable disable to disable the boost signal when the output voltage approaches its final value. Thus, the boost circuit provides a temporary boost current until the output voltage reaches its desired value.

Abstract: A voltage of an intensity corresponding to information to be recorded is applied to a recording medium which comprises a film containing a charge generating material. The film is sandwiched between two electrodes. Electric charges are accumulated in the recording medium upon application of the voltage so that information is recorded. When light is irradiated to the recording medium, the stored charges are converted into photo-current. The recorded information is read out by detecting the photo-current. When the electrodes are short-circuited, the recorded information is erased.

Abstract: A reference voltage circuit includes a self-decoupling boost circuit coupled between a supply voltage and an output node. The boost circuit provides a boost current to accelerate the transition of the output node's voltage. The boost circuit is controlled by a voltage detection circuit having its input coupled to the output node of the reference voltage circuit. The voltage detection circuit monitors the output voltage of the reference voltage circuit and provides a disable signal to disable the boost signal when the output voltage approaches its final value. Thus, the boost circuit provides a temporary boost current until the output voltage reaches its desired value.

Abstract: A method and apparatus for performing a specified test on a semiconductor memory device having a clock generating circuit and a control circuit in which the clock generating circuit generates a clock signal in response to an operation request signal and the control circuit generates a reset signal for stopping generation of the clock signal after a predetermined period of time. The control circuit also generates at least one operation control signal for performing a fundamental operation of the memory device in response to the clock signal. The test is performed by inputting a test mode signal to the semiconductor memory device to initiate the specified test, delaying generation of the reset signal for a period of time exceeding the predetermined period of time, carrying out the specified test while the test mode signal is being input, and terminating the specified test by stopping input of the test mode signal.