Abstract: The power consumed by repetitive switching and precharging of a DRAM bus during repetitive write cycles is reduced by latching the data lines to the DRAM array during repeated data writes in a way which avoids the necessity of precharging the lines before every write. A fast write mode is invoked when repeated writes are to occur and is cleared at the end of the repeated writes.

Abstract: A circuit for switching of power supply voltages in electrically programmable and erasable non-volatile semiconductor memory devices including a first switch-regulator block connected to a main power supply line with a programming voltage to generate a first programming voltage signal to be supplied to a memory device on a first programming line and a second switch-regulator block powered by the first programming line and designed to generate a second programming voltage to be supplied to the memory device on a second programming line. There is also provided a detector block connected to the first programming line to detect a reaching of a predetermined high level on the rising front of the first programming voltage signal and a reaching of a predetermined low level on the falling front of the first programming voltage signal and to emit at an output a corresponding enablement signal for a third regulator block located downstream.