Patents Examined by Hong Chong Kim
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Patent number: 7404054Abstract: A device with a small number of circuits is provided for blocking illegal address access from a bus master device connected to the processor system bus. An illegal address blocking circuit is inserted into the address line and control lines between the bus master device and the bus or the bus control circuit, according to the system bus configuration. A register is installed within the illegal address access blocking device to set an address range where access is allowed. The address output from the address line is then checked by a comparator to find if it is within the allowable range or not, and if it is outside the allowable range, then that illegal access is prevented by blocking the output on the control line.Type: GrantFiled: May 5, 2004Date of Patent: July 22, 2008Assignee: Renesas Technology Corp.Inventor: Yuki Kondoh
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Patent number: 7149860Abstract: In the case in which data in a storage system A is remotely copied to a storage system B, it is not taken into account whether the data of the remote copy is WORM data. In the case in which a setting is made such that data stored in a volume in the storage system A is copied to a volume in the storage system B, storage system A judges whether an attribute to the effect that data can be referred to and can be updated or to the effect that data can be referred to but cannot be updated is added to the volume in the storage system A. Then, if the volume is a volume to which the attribute to the effect that data can be referred to but cannot be updated is added, such attribute is added to the volume in the storage system B.Type: GrantFiled: July 6, 2004Date of Patent: December 12, 2006Assignee: Hitachi, Ltd.Inventors: Yusuke Nonaka, Naoto Matsunami, Akira Nishimoto, Yoichi Mizuno
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Patent number: 7143238Abstract: A computer system includes a central processing unit (CPU) and a cache memory coupled to the CPU. The cache memory includes a plurality of compressible cache lines to store additional data.Type: GrantFiled: September 30, 2003Date of Patent: November 28, 2006Assignee: Intel CorporationInventors: Ali-Reza Adl-Tabatabai, Anwar M. Ghuloum, Ram Huggahalli, Chris J. Newburn
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Patent number: 7136960Abstract: An integrated circuit chip is provided having a port for receiving a character string. A hardware hashing circuit on the integrated circuit chip is configured to perform a hashing function on the character string, thereby creating a hashed output value. A binary content addressable memory (CAM) array on the integrated circuit chip is coupled to receive the hashed output value. The binary CAM array provides an index value in response to the hashed output value if the hashed output value matches an entry of the binary CAM array. In a particular embodiment, the hardware hashing circuit can be configured to process character strings having different lengths (greater than the width of the binary CAM array) in response to one or more configuration bits. The hardware hashing circuit can include, an input register, Data Encryption Standard (DES) circuitry and exclusive OR circuitry.Type: GrantFiled: June 14, 2002Date of Patent: November 14, 2006Assignee: Integrated Device Technology, Inc.Inventor: David Honig
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Patent number: 7080222Abstract: A static random-access memory (SRAM) provides volatile storage of data in a cellular telephone. Connected to the volatile SRAM is a second SRAM that provides nonvolatile storage of data by backup battery means. Writing and reading of either volatile or nonvolatile data can occur. Additionally, provision is made to automatically back up data written to the volatile SRAM in the nonvolatile SRAM, as well as to streamline restoration of backed-up data from the nonvolatile SRAM to the volatile SRAM.Type: GrantFiled: September 20, 2002Date of Patent: July 18, 2006Assignee: Cypress Semiconductor Corp.Inventors: Kannan Srinivasagam, Rajesh Manapat, Mario Martinez
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Patent number: 7076609Abstract: Cache sharing for a chip multiprocessor. In one embodiment, a disclosed apparatus includes multiple processor cores, each having an associated cache. A control mechanism is provided to allow sharing between caches that are associated with individual processor cores.Type: GrantFiled: September 20, 2002Date of Patent: July 11, 2006Assignee: Intel CorporationInventors: Vivek Garg, Jagannath Keshava
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Patent number: 7062617Abstract: A method and apparatus for satisfying load operations by accessing data from a store buffer is described herein. It is a further goal of the present invention to satisfy load operations faster than prior art techniques in most cases. Finally, it is a goal of the present invention to provide an improved technique for satisfying load operations that does not significantly impact processor performance in the event that a present load is not satisfied within a predetermined amount of time.Type: GrantFiled: March 26, 2002Date of Patent: June 13, 2006Assignee: Intel CorporationInventor: James David Dundas
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Patent number: 7054994Abstract: A method and system for storing arranged data in a memory, the system including: (a) a plurality of random access memories, each random access memory (RAM) of the plurality including: (i) a first array of cells, the first array having at least two dimensions and having rows and columns, the first array designed and configured to contain a plurality of key entries, each of the cells having a unique address including a row index and a column index, each of the key entries for matching with an input key, and (b) a processor designed and configured to search the plurality of key entries for a match, in response to the input key, the plurality of RAMs designed and configured such that: (i) at least one row in a second of the RAMs has a row index that is identical to a row index in a first of the RAMs, and (ii) the key entries are arranged within each of the plurality of RAMs in monotonic order.Type: GrantFiled: July 29, 2002Date of Patent: May 30, 2006Assignee: Hy Wire Ltd.Inventors: Shay Kastoriano, Moshe Hershkovich, Guy Itzkovsky, Mor Levi, Eyal Shachrai, Yoram Stern, Moshe Stark
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Patent number: 7051184Abstract: One embodiment of the present invention provides a system for mapping memory addresses to cache entries. The system operates by first receiving a memory request at the cache memory, wherein the memory request includes a memory address. The system then partitions the memory address into a set of word offset bits and a set of higher-order bits. Next, the system maps the memory address to a cache entry by computing a modulo operation on the higher-order bits with respect to an integer and using the result as the cache index.Type: GrantFiled: June 4, 2003Date of Patent: May 23, 2006Assignee: SUN Microsystems, Inc.Inventor: Robert M. Lane
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Patent number: 7035993Abstract: A flash memory configuration and access method having a particular conversion method that uses the page or the sector in each flash memory block instead of the block that is commonly used as the base of the data conversion storage to store data. When data is written into the physical flash block of the flash memory, the original logic sector information can be preserved. The data is written into the same block of the flash memory in a manner according to the sequence as it is received instead of the sequence of the logic sector. Therefore, the block position does not move to refresh the block content until the physical block is full. Consequently, the number of times to move the physical block of the flash memory can be reduced to increase the lifetime of the flash memory. Moreover, since the number of times to erase is reduced, so that the writing speed can speed up to improve the operation efficiency.Type: GrantFiled: April 8, 2002Date of Patent: April 25, 2006Assignee: SimpleTech, Inc.Inventors: Shih-Chieh Tai, Chien-Hung Wu
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Patent number: 7003635Abstract: A system and method provides active inheritance on memory writes such that entities issuing later writes ensure that the effects of earlier writes to the same memory block will be seen. A write chain is preferably formed by storing information and state in miss address file (MAF) entries maintained by the entities. The write chain links the entities requesting write access to the memory block. When the desired memory block becomes available, the information and state stored at the MAF entries is then utilized by each entity in ensuring that all earlier writes are complete before its write is allowed to complete.Type: GrantFiled: October 3, 2002Date of Patent: February 21, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventor: Stephen R. Van Doren
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Patent number: 7003637Abstract: In a disk control device arranged to include a CPU, a plurality of channel control units, a plurality of disk control units, a cache memory, and a data transfer integrated circuit communicably connected to the cache memory via a plurality of data buses, when receiving a request for access to the cache memory from any one of the CPU, the channel control units and the disk control units, the data transfer integrated circuit provides access to the cache memory by use of a certain number of one or ones of the data buses, which number is determinable in accordance with a transfer data length that is set in the access request.Type: GrantFiled: January 30, 2004Date of Patent: February 21, 2006Assignee: Hitachi, Ltd.Inventors: Xiaoming Jiang, Satoshi Yagi, Ikuya Yagisawa
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Patent number: 6976119Abstract: A method of passing a location of a data interface. The method involves storing a first pointer in an architected location for locating information related to a system firmware read only memory (ROM). A portion of memory is allocated for a data structure that is an interface for handing off system component information. A second pointer is stored in a memory location pointed to by the first pointer. The second pointer points to the data structure.Type: GrantFiled: June 14, 2002Date of Patent: December 13, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Shiraz Ali Qureshi, Martin O. Nicholes
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Patent number: 6502164Abstract: A method for transmitting a data of a disk recording medium including: a first step of reading file management information for managing a data recorded in a file structure in a disk recording medium; a second of storing the read file management information in a storing unit different to the recording medium; and a third step of reading and transmitting a corresponding file management information as stored in the storing unit when the file management information is requested. By doing that, the file management information that is frequently requested to be transferred, such as a file system data managing a data in a file structure recorded in a disk recording medium such as a CD-ROM, is stored in a specific storing area so as to be quickly read and transmitted to a connected instrument such as a personal computer, without performing a tracking servo operation to drive a sled motor. Thus, the transfer rate of the optical disk driver such as the CD-ROM can be highly improved.Type: GrantFiled: September 14, 2000Date of Patent: December 31, 2002Assignee: LG Electronics Inc.Inventor: Cheol Young Choi
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Patent number: 6502169Abstract: A system and method for detecting block(s)of data transferred to a disk array from a host processor system, in which the block(s) have unique, identifiable values or patterns, is provided. A direct memory access (DMA) engine is resident on the bus structure between the host and the disk array, which can be configured as a redundant array of independent disks (RAID). A cache memory is also resident on the bus and is adapted to cache write data from the host under control of a cache manager prior to storage thereof in the disk array. The DMA engine is adapted to detect predetermined patterns of data as such data is transferred over the bus therethrough. Such data can include a series of consecutive zeroes or another repetitive pattern.Type: GrantFiled: June 27, 2000Date of Patent: December 31, 2002Assignee: Adaptec, Inc.Inventor: Eric S. Noya
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Patent number: 6499089Abstract: A circuit generally comprising a memory and a logic circuit. The memory may comprise (i) a first section configured to (a) read and write data and (b) have a first configurable size and (ii) a second section configured to (a) read and write data independently of the first section and (b) have a second configurable size. The logic circuit may be configured to control the first configurable size and the second configurable size.Type: GrantFiled: January 18, 2000Date of Patent: December 24, 2002Assignee: Cypress Semiconductor Corp.Inventors: Cathal G. Phelan, Scott Harmel, Rajesh Manapat, Sunil Kumar Koduru
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Patent number: 6470438Abstract: In one embodiment of the invention, each data value which is provided to a non-tagged, n-way cache is hashed with a number of bits which correspond to the data value, thereby producing a hashed data value. Preferably, the bits which are hashed with the data value are address bits. The hashed data value is then written into one or more ways of the cache using index hashing. A cache hit signal is produced using index hashing and voting. In a cache where data values assume only a few different values, or in a cache where many data values which are written to the cache tend to assume a small number of data values, data hashing helps to reduce false hits by insuring that the same data values will produce different hashed data values when the same data values are associated with different addresses. In another embodiment of the invention, data values which are provided to a non-tagged, n-way cache are written into the cache in a non-count form.Type: GrantFiled: February 22, 2000Date of Patent: October 22, 2002Assignee: Hewlett-Packard CompanyInventor: James E McCormick, Jr.