Abstract: A substrate processing method capable of stably loading a substrate regardless of a variation in pressure of a reaction space includes supplying an inert gas; and forming a thin film by sequentially and repeatedly supplying a source gas, supplying a reaction gas, and activating the reaction gas, wherein a center portion of a substrate and a center portion of a susceptor are spaced apart from each other to form a separate space, the reaction space above the substrate and the separate space communicate with each other via one or more channels, an inert gas is introduced to the separate space through the one or more channels during the supplying of the inert gas, and the inert gas prevents pressure imbalance between the separate space and the reaction space during a thin film deposition process.

Abstract: A stirrer includes a magnetic bar and a microwave absorbing layer around the magnetic bar. The stirrer absorbs a microwave and converts the microwave to thermal energy to heat the mixed solution reactant.

Abstract: A 3D memory array includes a row of stacks, each stack having alternating gate strips and dielectric strips. Dielectric plugs are disposed between the stacks and define cell areas. A data storage film and a channel film are disposed adjacent the stacks on the sides of the cell areas. The middles of the cell areas are filled with an intracell dielectric. Source lines and drain lines form vias through the intracell dielectric. The source lines and the drain lines are each provided with a bulge toward the interior of the cell area. The bulges increase the areas of the source line and the drain line without reducing the channel lengths. In some of these teachings, the areas of the source lines and the drain lines are increased by restricting the data storage film or the channel layer to the sides of the cell areas adjacent the stacks.

Abstract: A method for depositing a silicon nitride layer on a stack is provided. The method comprises providing an atomic layer deposition, comprising a plurality of cycles, wherein each cycle comprises dosing the stack with a silicon containing precursor by providing a silicon containing precursor gas, providing an N2 plasma conversion, and providing an H2 plasma conversion.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a plurality of nanowire structures over a channel region of a semiconductor fin structure, a source/drain feature on a source/drain region of the semiconductor fin structure, and a dielectric fin structure spaced apart from the source/drain feature and the semiconductor fin structure. A top surface of the dielectric fin structure is higher than a top surface of a bottommost one of the nanowire structures, and a bottom surface of the dielectric fin structure is lower than a bottom surface of the source/drain feature.

Abstract: A high-speed layout device for a photovoltaic module includes a module input unit, a module output unit, a tray transfer unit, and a layout transfer unit. The tray transfer unit extends into a position below the module input unit to lift the photovoltaic module, moves horizontally, places the photovoltaic module on the module output unit for outputting, and then returns to the position below the module input unit. A layout of a middle row of battery strings is performed on the tray transfer unit, a layout of a first row of battery strings is performed on the input unit or the tray transfer unit, and a layout of a last row of battery strings is performed on the tray transfer unit or the output unit, wherein the layout of the first row of battery strings and the layout of the last row of battery strings are performed on different units.

Abstract: A method of making an acoustic sensor (e.g., for use in a piezoelectric MEMS microphone) includes forming or providing a mold having one or more grooves in a top surface of the mold that extend in a direction of the length of the mold to a distal end of the mold. The method also includes forming or depositing a structure having one or more piezoelectric layers over the top surface of the mold to define a beam, the distal portion of the beam having a corrugated section including one or more grooves that correspond to the grooves of the mold. The method also includes forming a gap in the structure to define two beams separated by the gap, and releasing the structure from the mold to form one or more cantilever beams that increases an acoustic resistance of the gap between sensors.

Abstract: A semiconductor device includes a substrate, first word lines and second word lines; one or more first word line trenches and one or more second word line trenches are alternately arranged on the substrate in parallel; each first word line is arranged in a respective first word line trench; each second word line is arranged in a respective second word line trench, where width of the first word line trench is greater than width of the second word line trench, and depth of the first word line trench is less than depth of the second word line trench, so that width of the first word line is greater than width of the second word line, height of the first word line is less than height of the second word line, and threshold voltage of the first word line is greater than threshold voltage of the second word line.

Abstract: A manufacturing method of a semiconductor device includes forming a stack of first semiconductor layers and second semiconductor layers alternatively formed on top of one another, where a topmost layer of the stack is one of the second semiconductor layers; forming a patterned mask layer on the topmost layer of the stack; forming a trench in the stack based on the patterned mask layer to form a fin structure; forming a cladding layer extending along sidewalls of the fin structure; and removing the patterned mask layer and a portion of the cladding layer by performing a two-step etching process, where the portion of the cladding layer is removed to form cladding spacers having a concave top surface with a recess depth increasing from the sidewalls of the fin structure.

Abstract: Embodiments of the present application relate to the field of semiconductors, and provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, including active regions arranged at intervals and an isolation structure located between the active regions; a word line (WL) trench, penetrating through the active region and the isolation structure along a first direction; and a WL, located in the WL trench, wherein on a section in a second direction, a first height difference is formed between the active region and the isolation structure; and the second direction is parallel to the substrate and perpendicular to the first direction.

Abstract: A manufacturing method of a semiconductor device includes forming an opening in a substrate, implanting a dopant in the substrate from a sidewall of the opening such that a doping region is formed in the substrate at the sidewall of the opening, filling a dielectric material in the opening to form a first dielectric structure after implanting the dopant in the substrate from the sidewall of the opening, and forming a passing word line in the dielectric structure.

Abstract: The present disclosure provides a semiconductor device, a method of manufacturing a semiconductor device and an electronic device. The method of manufacturing a semiconductor device includes: forming word line trenches on a semiconductor substrate, forming a word line structure in each of the word line trenches, and finally forming active regions. The word line trenches pass through the semiconductor substrate without passing through other material.

Abstract: A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.

Abstract: Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.

Abstract: A substrate processing apparatus includes a chamber including an upper chamber and a lower chamber coupled to each other to provide a space for processing a substrate, a substrate support configured to support the substrate within the chamber, an upper supply port provided in the upper chamber and configured to supply a supercritical fluid on an upper surface of the substrate within the chamber, a recess provided in a lower surface of the upper chamber, the recess including a horizontal extension portion extending in a direction parallel with the upper surface of the substrate in a radial direction from an outlet of the upper supply port and an inclined extension portion extending obliquely at an angle from the horizontal extension portion, and a baffle member disposed within the recess between the upper supply port and the substrate.

Abstract: A method of forming a microelectronic device comprises forming a memory array region comprising memory cells vertically over a base structure comprising a semiconductive material and alignment mark structures vertically extending into the semiconductive material. First contact structures are formed to extend through the memory array region and into the alignment mark structures. A support structure is formed over the memory array region. A portion of the base structure is removed to expose the alignment mark structures. A control logic region is formed vertically adjacent a remaining portion of the base structure. The control logic region comprises control logic devices in electrical communication with the first contact structures by way of second contact structures extending partially through the alignment mark structures and contacting the first contact structures. Microelectronic devices, memory devices, electronic systems, and additional methods are also described.

Abstract: A vertical memory device includes a substrate with a cell region, a through via region on opposite sides of the cell region, and a mold region surrounding the cell and through via regions, gate electrodes spaced apart from each other along a first direction vertical to an upper surface of the substrate, and extending in a second direction parallel to the upper surface of the substrate, a channel extending in the first direction on the cell region, and extending through at least a portion of the stacked gate electrodes, and a first mold including first and second layers alternately and repeatedly stacked along the first direction on the mold region, the first and second layers including different insulation materials from each other, and each of the second layers of the first mold being at the same height as and contact a corresponding one of the gate electrodes.

Abstract: The present invention addresses uniformly formed layers on TCOs with minimized thickness which are hole transporting, due to a hole transport material which is configured for self assembly on the corresponding surface. The layers are formed by a compound made up of at least one kind of molecule according to formula (I) mixed up with a filler molecule FM given by where L is a linking fragment, A an anchor group and HTF is a hole transporting fragment. FM (filler molecule) is at least one kind of molecule consisting of an anchoring group, an alkyl chain of N carbon atoms, with N is in the range of 1 to 18, and a functional group of at least on of the group methyl, halogen, amino, bromide, ammonium and sulfuric functional group and where x is in the range of 0.02 to 1 and y equals (1?x).

Abstract: A semiconductor device includes a substrate including an active region defined by an isolation layer; a buried gate structure provided in a trench formed in the substrate; and a first doped region and a second doped region formed in the active region and separated by the trench, wherein the buried gate structure includes a gate dielectric layer conformally covering the trench; and a gate electrode including a first portion partially filling the trench on the gate dielectric layer and a second portion formed on the first portion, wherein the second portion includes a material included in the first portion and dopants including phosphorous (P), germanium (Ge), or a combination thereof, and wherein the first portion does not laterally overlap with the doped region and the second doped region, and all or a part of the second portion laterally overlaps with the first doped region and the second doped region.

Abstract: A method for evaluating electrical characteristics of a semiconductor substrate, the method including the steps of: forming a p-n junction on a surface of the semiconductor substrate; mounting the semiconductor substrate on a wafer chuck provided with an equipment for performing light irradiation on the surface of the semiconductor substrate and an equipment for measuring the quantity of the light for the irradiation; performing light irradiation on the surface of the semiconductor substrate for a predetermined time; and measuring an amount of carriers generated after the light irradiation of the p-n junction at least after turning off the light irradiation. This provides a method for evaluating a semiconductor substrate that allows the same evaluation in a wafer state as when an actual solid-state image sensor has been formed without producing a device by using process equipment when evaluating characteristics corresponding to residual image characteristics of a wafer.