Patents Examined by Hsien Ming Lee
  • Patent number: 10971581
    Abstract: A semiconductor device has transistors formed on a substrate and including first and second impurity regions of a first conductivity type, a guard ring of a second conductivity type formed on the substrate and surrounding the transistors in a plan view, a wiring formed on and electrically connected to the guard ring, and a ground wiring formed on the wiring and electrically connected to the wiring and the second impurity region. In a plan view, the transistor includes a first part having a distance that is a first distance from the guard ring, and a second part having a distance that is a second distance shorter than the first distance from the guard ring. In a plan view, the first part is located at a position separated from the ground wiring, and the second part is located at a position overlapping the ground wiring.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: April 6, 2021
    Assignee: SOCIONEXT INC.
    Inventor: Hidetoshi Tanaka
  • Patent number: 10964888
    Abstract: The present disclosure describes a method utilizing an ion beam etch process, instead of a RIE etch process, to form magnetic tunnel junction (MTJ) structures. For example, the method includes forming MTJ structure layers on an interconnect layer, where the interconnect layer includes a first area and a second area. The method further includes depositing a mask layer over the MTJ structure layers in the first area and forming masking structures over the MTJ structure layers in the second area. The method also includes etching with an ion beam etch process, the MTJ structure layers between the masking structures to form MTJ structures over vias in the second area of the interconnect layer; and removing, with the ion beam etch process, the mask layer, the top electrode, the MTJ stack, and a portion of the bottom electrode in the first area of the interconnect layer.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pin-Ren Dai, Chung-Ju Lee, Chung-Te Lin, Chih-Wei Lu, Hsi-Wen Tien, Tai-Yen Peng, Chien-Min Lee, Wei-Hao Liao
  • Patent number: 10964685
    Abstract: An integrated circuit includes a cell layer, a first metal layer, a first conductive via, and a second conductive via. The cell layer includes first and second cells, in which the first cell is separated from the second cell by a non-zero distance. The first metal layer includes a first conductive feature and a second conductive feature, the first conductive feature overlaps the first cell and does not overlap the second cell, and the second conductive feature overlaps the second cell and does not overlap the first cell, in which the first conductive feature is aligned with the second conductive feature along lengthwise directions of the first and second conductive features. The first conductive via interconnects the cell layer and the first conductive feature of the first metal layer. The second conductive via interconnects the cell layer and the second conductive feature of the first metal layer.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fong-Yuan Chang, Kuo-Nan Yang, Chung-Hsing Wang, Lee-Chung Lu, Sheng-Fong Chen, Po-Hsiang Huang, Hiranmay Biswas, Sheng-Hsiung Chen, Aftab Alam Khan
  • Patent number: 10964603
    Abstract: A method of forming a semiconductor structure includes forming one or more vertical fins each including a first semiconductor layer providing a vertical transport channel for a lower vertical transport field-effect transistor (VTFET) of a stacked VTFET structure, an isolation layer over the first semiconductor layer, and a second semiconductor layer over the isolation layer providing a vertical transport channel for an upper VTFET of the stacked VTFET structure. The method also includes forming a first gate stack including a first gate dielectric layer and a first gate conductor layer surrounding a portion of the first semiconductor layer of the vertical fins. The method further includes forming a second gate stack including a second gate dielectric layer and a second gate conductor layer surrounding a portion of the second semiconductor layer of the vertical fins. The first gate conductor layer and the second gate conductor layer are the same material.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: March 30, 2021
    Assignee: International Business Machines Corporation
    Inventors: Tenko Yamashita, Takashi Ando, Oleg Gluschenkov, Chen Zhang, Koji Watanabe
  • Patent number: 10964823
    Abstract: A semiconductor structure and a method for forming same are provided. One form of the method includes: providing a substrate including a device unit area, where at least two fins are formed on the substrate, a channel structure layer is formed on the fins, which includes a first channel structure layer located on at least one fin, a second channel structure layer located on at least one fin, and a third channel structure layer located on at least one fin, the first channel structure layer includes multiple channel laminates, each channel laminate includes a first sacrificial layer and a first channel layer; forming a dummy gate structure across the channel structure layer; forming a source-drain doping layer on two sides of the dummy gate structure; and forming a gate structure at positions of the dummy gate structure and the first sacrificial layer.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: March 30, 2021
    Assignees: Semiconductor Manufacturing (Beijing) International Corporation, Semiconductor Manufacturing (Shanghai) International Corporation
    Inventor: Nan Wang
  • Patent number: 10950169
    Abstract: An organic light emitting diode display includes a substrate. The substrate defines a first pixel portion and one or more second pixel portions. Pixels formed in the first pixel portion include at least some transparent organic light emitting diode pixels, while other pixels formed in the one or more second pixel portions include only reflective organic light emitting diode pixels.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: March 16, 2021
    Assignee: Motorola Mobility LLC
    Inventor: Ye Yang
  • Patent number: 10950536
    Abstract: An apparatus is described. The apparatus includes an electro-mechanical interface having angled signal interconnects, wherein, the angling of the signal interconnects is to reduce noise coupling between the angled signal interconnects.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Zhen Zhou, Jun Liao, Xiang Li, Kevin Stone, Daqiao Du, Tae-Young Yang, Ling Zheng, James A. McCall
  • Patent number: 10944016
    Abstract: An optical detection unit includes a first wiring substrate that has a first main surface, a plurality of optical detection chips that each have a light receiving surface and a rear surface on a side opposite to the light receiving surface and are two-dimensionally arranged on the first main surface, a first bump electrode that electrically connects the optical detection chip to the first wiring substrate, a light transmitting portion that is provided on the light receiving surface, and a light shielding portion that has light reflection properties or light absorption properties. The optical detection chip includes a Geiger-mode APD and is mounted on the first wiring substrate by the first bump electrode in a state in which the rear surface faces the first main surface.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: March 9, 2021
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Ryutaro Tsuchiya, Terumasa Nagano, Yuta Tsuji, Go Kawai, Yuki Okuwa
  • Patent number: 10943815
    Abstract: A substrate for microelectronic radiofrequency devices includes a carrier substrate made of a first semiconductor material having a resistivity higher than 500 ohms-cm; a plurality of trenches in the carrier substrate, which trenches are filled with a second material, and defining on a first side of the carrier substrate a plurality of first zones made of a first material and at least one second zone made of a second material. The second material has a resistivity higher than 10 kohms-cm, and the first zones have a maximum dimension smaller than 10 microns and are insulated from one another by the second zone.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: March 9, 2021
    Assignee: Soitec
    Inventors: Eric Desbonnets, Ionut Radu, Oleg Kononchuk, Jean-Pierre Raskin
  • Patent number: 10943901
    Abstract: A representative method for manufacturing fin field-effect transistors (FinFETs) includes steps of forming a plurality of fin structures over a substrate, and forming a plurality of isolation structures interposed between adjacent pairs of fin structures. Upper portions of the fin and isolation structures are etched. Epitaxial structures are formed over respective fin structures, with each of the epitaxial structures adjoining adjacent epitaxial structures. A dielectric layer is deposited over the plurality of epitaxial structures with void regions formed in the dielectric layer. The void regions are interposed between adjacent pairs of fin structures.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: March 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10944047
    Abstract: Thermally activated memristors from solution-processed two-dimensional (2D) semiconductors, fabricating methods and applications of the same. The memristor includes a semiconductor film formed on a nanoporous membrane, and at least two electrodes spatial-apart formed on the semiconductor film and electrically coupled with the semiconductor film to define a channel in the semiconductor film between the at least two electrodes, where the channel has one or more filaments, one or more dendrite, or a combination of them formed in the semiconductor film. The underlying switching mechanism applies generally to a range of 2D semiconductors including, but not limited to, MoS2, MoSe2, WS2, ReS2, InSe, or related 2D semiconductor materials.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: March 9, 2021
    Assignee: NORTHWESTERN UNIVERSITY
    Inventors: Mark C. Hersam, Vinod K. Sangwan
  • Patent number: 10943900
    Abstract: A semiconductor device is provided. The Semiconductor device includes a substrate, a first fin type pattern and a second fin type pattern which protrude from an upper surface of the substrate and are spaced apart from each other, a first semiconductor pattern on the first fin type pattern, a second semiconductor pattern on the second tin type pattern and a blocking pattern between the first semiconductor pattern and the second semiconductor pattern, a part of the first semiconductor pattern being inserted in the blocking pattern.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: March 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun Chul Sagong, Sang Woo Pae, Ki Hyun Choi, June Kyun Park, Uk Jin Jung
  • Patent number: 10943864
    Abstract: A device and method of utilizing a programmable redistribution die to redistribute the outputs of semiconductor dies. Integrated circuit packages using a programmable redistribution die are shown. Methods of creating a programmable redistribution die are shown.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Min Suet Lim, J-Wing Teh, Bok Eng Cheah
  • Patent number: 10943966
    Abstract: Provided is a display device including a plurality of pixels at least one of which has a first transistor and a light-emitting element. The first transistor includes a gate electrode, a gate insulating film over the gate electrode, an oxide semiconductor film over the gate insulating film, and a first terminal and a second terminal electrically connected to the semiconductor film. The second terminal is electrically connected to the light-emitting element. A region in which the first terminal overlaps with the gate electrode can be smaller than a region in which the second terminal overlaps with the gate electrode.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: March 9, 2021
    Assignee: Japan Display Inc.
    Inventors: Tetsuo Morita, Hiroyuki Kimura, Makoto Shibusawa, Hiroshi Tabatake, Yasuhiro Ogawa
  • Patent number: 10936944
    Abstract: A neuromorphic device includes a first electrode layer arranged on a substrate, and an electrolyte layer arranged on the first electrode layer. The electrolyte layer includes a solid electrolyte material. The neuromorphic device further includes an ion permeable, electrically conductive membrane arranged on the electrolyte layer and an ion intercalation layer arranged on the ion permeable, electrically conductive membrane. The neuromorphic device includes a second electrode layer arranged on the ion intercalation layer.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: March 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Teodor K. Todorov, John Rozen, Douglas M. Bishop
  • Patent number: 10937686
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having an enhanced gap fill layer in trenches. The present disclosure provides a novel gap fill layer formed using a multi-step deposition and in-situ treatment process. The deposition process can be a flowable chemical vapor deposition (FCVD) utilizing one or more assist gases and molecules of low reactive sticking coefficient (RSC). The treatment process can be an in-situ process after the deposition process and includes exposing the deposited gap fill layer to plasma activated assist gas. The assist gas can be formed of ammonia. The low RSC molecule can be formed of trisilylamin (TSA) or perhydropolysilazane (PHPS).
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: March 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jian-Shiou Huang, Bang-Tai Tang, Chih-Tang Peng, Tai-Chun Huang, Yen-Chun Huang
  • Patent number: 10930670
    Abstract: A semiconductor device, and a method of manufacturing the semiconductor device, the method includes forming a first stack structure penetrated by first channel structures, forming electrode patterns surrounding second channel structures and separated from each other by first slits and second slits, the second channel structures coupled to the first channel structures, and the second slits comprising a different width from the first slits, filling each of the first slits and the second slits with an insulating material to cover sidewalls of the electrode patterns, and forming third slits passing through the insulating material in each of the second slits and extending to pass through the first stack structure.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: February 23, 2021
    Assignee: SK hynix Inc.
    Inventors: Wan Sup Shin, Ki Hong Lee, Jae Jung Lee, Young Geun Jang
  • Patent number: 10930733
    Abstract: Hydrogen atoms and crystal defects are introduced into an n? semiconductor substrate by proton implantation. The crystal defects are generated in the n? semiconductor substrate by electron beam irradiation before or after the proton implantation. Then, a heat treatment for generating donors is performed. The amount of crystal defects is appropriately controlled during the heat treatment for generating donors to increase a donor generation rate. In addition, when the heat treatment for generating donors ends, the crystal defects formed by the electron beam irradiation and the proton implantation are recovered and controlled to an appropriate amount of crystal defects. Therefore, for example, it is possible to improve a breakdown voltage and reduce a leakage current.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: February 23, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takashi Yoshimura, Masayuki Miyazaki, Hiroshi Takishita, Hidenao Kuribayashi
  • Patent number: 10920140
    Abstract: Provided is a method for producing a fluorescent material, including: preparing a raw material mixture including a compound containing at least one rare earth element Ln selected from the group consisting of Y, Gd, La, Lu, Sc and Sm, a compound containing at least one Group 13 element selected from Al and Ga, a compound containing Tb, a compound containing Ce and a compound containing Eu, wherein the raw material mixture contains each compound such that each element satisfies a composition represented by the following formula (I): (Ln1-a-b-cTbaCebEUc)3(Al1-dGad)5O12 (I), wherein a, b, c and d satisfy 0.25?a<1, 0.008×10?2?b?1.5×10?2, 0.012×10?2?c?2×10?2, and 0?d?0.85, and heat-treating the raw material mixture to obtain the fluorescent material.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: February 16, 2021
    Assignee: NICHIA CORPORATION
    Inventor: Tomokazu Suzuki
  • Patent number: 10923523
    Abstract: In one example, an apparatus comprises: a first photodiode configured to convert a first component of light to a first charge, second photodiode configured to convert a second component of the light to a second charge; and an interface circuit configured to: perform a first quantization and a second quantization of the first charge to generate, respectively, a first result and a second result, the first quantization and the second quantization being associated with different light intensity ranges; provide one of the first result or the second result to represent an intensity of the first component of a pixel; perform the first quantization and the second quantization of the second charge to generate, respectively, a third result and a fourth result; and provide one of the third result or the fourth result to represent an intensity of the second component of the pixel.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: February 16, 2021
    Assignee: Facebook Technologies, LLC
    Inventors: Xinqiao Liu, Song Chen