Patents Examined by Hsien Ming Lee
  • Patent number: 11450679
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings and support openings are formed through the alternating stack, and memory opening fill structures and support pillar structures are formed in the memory openings and in the support openings, respectively. Via cavities extending to each of the sacrificial material layers are formed through the alternating stack without forming any stepped surfaces in the alternating stack. The via cavities may be formed in areas that do not overlap with the support pillar structures, or in areas that include at least one support pillar structure. Sacrificial via fill structures are formed in the via cavies, and the sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are removed, and a combination of a tubular dielectric spacer and a contact via structure can be formed in the via cavities.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: September 20, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yoshinobu Tanaka, Koichi Ito, Hideaki Hasegawa, Akihiro Tobioka, Sung Tae Lee
  • Patent number: 11450604
    Abstract: Embodiments of 3D memory devices having staircase structures and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory array structure and a staircase structure in an intermediate of the memory array structure. The staircase structure includes a plurality of stairs extending along the lateral direction, and a bridge structure in contact with the first memory array structure and the second memory array structure. The plurality of stairs includes a stair above one or more dielectric pairs The stair includes a conductor portion on a top surface of the stair and in contact with and electrically connected to the bridge structure, and is electrically connected to at least one of a first memory array structure and a second memory array structure of the memory array structure through the bridge structure. Along a second lateral direction, a width of the conductor portion is unchanged.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: September 20, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Di Wang, Wenxi Zhou, Zhiliang Xia
  • Patent number: 11450528
    Abstract: A process for growing nanowires or nanopyramids comprising: (I) providing a graphitic substrate and depositing AlGaN, InGaN, AlN or AlGa(In)N on said graphitic substrate at an elevated temperature to form a buffer layer or nanoscale nucleation islands of said compounds; (II) growing a plurality of semiconducting group III-V nanowires or nanopyramids, preferably III-nitride nanowires or nanopyramids, on the said buffer layer or nucleation islands on the graphitic substrate, preferably via MOVPE or MBE.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: September 20, 2022
    Assignees: Crayonano As, Norwegian University Of Science And Technology (NTNU)
    Inventors: Dong Chul Kim, Ida Marie Høiaas, Mazid Munshi, Bjørn Ove Fimland, Helge Weman, Dingding Ren, Dasa Dheeraj
  • Patent number: 11443988
    Abstract: A method for manufacturing a semiconductor is provided. A first oxide layer is formed on a substrate. A first nitride layer is formed on the first oxide layer. A second oxide layer, a second nitride layer are formed on the first nitride layer. A polysilicon layer is formed on the second nitride layer. A third nitride layer is formed on the polysilicon layer. One or more first patterns are formed on the third nitride layer. The one or more first patterns are transferred to the polysilicon layer to form one or more patterned polysilicon layer. A portion of the first oxide layer, first nitride layer, second oxide layer, and second nitride layer are removed using the one or more patterned polysilicon layer as a first mask.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: September 13, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kyung Yub Jeon
  • Patent number: 11444165
    Abstract: Semiconductor devices and methods of forming the same include forming an inner spacer on a semiconductor fin. Two outer spacers are formed around the inner spacer, with one outer spacer being separated from the inner spacer by a gap. A dipole-forming layer is formed on the semiconductor fin in the gap. A gate stack is formed on the semiconductor fin, between the outer spacers.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: September 13, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Alexander Reznicek, Jingyun Zhang, Choonghyun Lee, Pouya Hashemi
  • Patent number: 11443977
    Abstract: A method (100) for forming a semiconductor structure (200) comprising a silicon-on-insulator layer structure with crystalline silicon oxide SiOx as the insulator material comprises: providing (120) a crystalline silicon substrate (201) having a substantially clean deposition surface (202) in a vacuum chamber; heating (130) the silicon substrate to an oxidation temperature To in the range of 550 to 1200, 550 to 1000, or 550 to 850° C.; supplying (140), while keeping the silicon substrate in the oxidation temperature, with an oxidation pressure Po in the range of 1·10?8 to 1·10?4 mbar in the vacuum chamber, molecular oxygen O2 into the vacuum chamber with an oxygen dose Do in the range of 0.1 to 1000 Langmuir; whereby a crystalline silicon oxide layer (204) with a thickness of at least two molecular layers is formed within the silicon substrate, between a crystalline silicon base layer (203) and a crystalline silicon top layer (205).
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: September 13, 2022
    Assignee: TURUN YLIOPISTO
    Inventors: Pekka Laukkanen, Mikhail Kuzmin, Jaakko Mäkelä, Marjukka Tuominen, Marko Punkkinen, Antti Lahti, Kalevi Kokko, Juha-Pekka Lehtiö
  • Patent number: 11444099
    Abstract: Microelectronic devices include a stack structure with a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. Conductive contact structures extend through the stack structure. An insulative material is between the conductive contact structures and the tiers of the stack structure. In a lower tier portion of the stack structure, a conductive structure, of the conductive structures, has a portion extending a first width between a pair of the conductive contact structures. In a portion of the stack structure above the lower tier portion, an additional conductive structure, of the conductive structures, has an additional portion extending a second width between the pair of the conductive contact structures. The second width is greater than the first width. Related methods and electronic systems are also disclosed.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: September 13, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Anilkumar Chandolu, Indra V. Chary
  • Patent number: 11437503
    Abstract: A semiconductor device includes first and second electrodes, a semiconductor part therebetween, and first and second control electrodes in a trench of the semiconductor part. The first and second control electrodes are arranged along a front surface of the semiconductor part. The semiconductor part includes first and third layers of a first-conductivity-type, and the second and fourth layer of a second-conductivity-type. The second layer is provided between the first layer and the second electrode. Between the second layer and the second electrode, the third and fourth layers are provided apart from the first layer with first and second portions of the second layer interposed, respectively. The first portion of the second layer has a first thickness in a second direction from the first electrode toward the second electrode. The second portion of the second layer has a second thickness in the second direction larger than the first thickness.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: September 6, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Takeshi Suwa, Tomoko Matsudai, Yoko Iwakaji
  • Patent number: 11437318
    Abstract: A microelectronic device comprises blocks, contact structures, filled vias, and a base structure. The blocks each have a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. Each block comprises a forward staircase structure and a reverse staircase structure. The contact structures are on steps of the forward staircase structure of a first of the blocks and on additional steps of the reverse staircase structure of a second of the blocks horizontally neighboring the first of the blocks. The filled vias extend through portions of the first of the blocks within horizontal boundaries of the reverse staircase structure of the first of the blocks and extend through portions of the second of the blocks within horizontal boundaries of the forward staircase structure of the second of the blocks. The base structure underlies the blocks and comprises transistors coupled to the filled vias.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: September 6, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Qui V. Nguyen, Chang H. Siau
  • Patent number: 11437391
    Abstract: A method of forming a microelectronic device comprises forming a stack structure. Pillar structures are formed to vertically extend through the stack structure. At least one trench and additional trenches are formed to substantially vertically extend through the stack structure. Each of the additional trenches comprises a first portion having a first width, and a second portion at a horizontal boundary of the first portion and having a second width greater than the first width. A dielectric structure is formed within the at least one trench and the additional trenches. The dielectric structure comprises at least one angled portion proximate the horizontal boundary of the first portion of at least some of the additional trenches. The at least one angled portion extends at an acute angle to each of a first direction and a second direction transverse to the first direction. Microelectronic devices and electronic systems are also described.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: September 6, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Raja Kumar Varma Manthena, Anilkumar Chandolu
  • Patent number: 11430732
    Abstract: A vertical memory device includes a cell stacked structure, a wiring connection structure, and a first insulating interlayer. The cell stacked structure may include insulation layers and gate patterns repeatedly and alternately stacked on a first region of a substrate. The wiring connection structure may contact side walls of the cell stacked structure. The wiring connection structure may include a first staircase structure having one side of a stepped shape, a second staircase structure having one side of a stepped shape and disposed below the first staircase structure, and a first dummy staircase structure between the first and second staircase structures. The first and second staircase structures may be spaced apart from each other in the first direction, and both sides in the first direction of the first dummy staircase structure may have stepped shapes. The first insulating interlayer may be on the substrate to cover the wiring connection structure.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: August 30, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seungjun Shin
  • Patent number: 11424154
    Abstract: A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: August 23, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lei-Chun Chou, Chih-Liang Chen, Jiann-Tyng Tzeng, Chih-Ming Lai, Ru-Gun Liu, Charles Chew-Yuen Young
  • Patent number: 11424243
    Abstract: In a method of manufacturing a semiconductor device, a separation wall made of a dielectric material is formed between two fin structures. A dummy gate structure is formed over the separation wall and the two fin structures. An interlayer dielectric (ILD) layer is formed over the dummy gate structure. An upper portion of the ILD layer is removed, thereby exposing the dummy gate structure. The dummy gate structure is replaced with a metal gate structure. A planarization operation is performed to expose the separation wall, thereby dividing the metal gate structure into a first gate structure and a second gate structure. The first gate structure and the second gate structure are separated by the separation wall.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: August 23, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Chih-Liang Chen, Shi Ning Ju
  • Patent number: 11417676
    Abstract: A method of forming a microelectronic device comprises forming a memory array region comprising memory cells vertically over a base structure comprising a semiconductive material and alignment mark structures vertically extending into the semiconductive material. First contact structures are formed to extend through the memory array region and into the alignment mark structures. A support structure is formed over the memory array region. A portion of the base structure is removed to expose the alignment mark structures. A control logic region is formed vertically adjacent a remaining portion of the base structure. The control logic region comprises control logic devices in electrical communication with the first contact structures by way of second contact structures extending partially through the alignment mark structures and contacting the first contact structures. Microelectronic devices, memory devices, electronic systems, and additional methods are also described.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: August 16, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Umberto Maria Meotto, Emilio Camerlenghi, Paolo Tessariol, Luca Laurin
  • Patent number: 11417603
    Abstract: A semiconductor device a substrate; conductive patterns on the substrate, the conductive patterns being spaced apart from each other in a vertical direction perpendicular to a surface of the substrate, and an edge of the conductive patterns including a step portion such that an end of one conductive pattern is not overlapped in the vertical direction with conductive patterns positioned thereover; insulation patterns between the conductive patterns; sidewall insulation patterns on the sidewalls of the conductive patterns to cover sidewalls of the conductive patterns; upper pad patterns on upper surfaces of the step portion of the conductive patterns and upper surfaces of a portion of the sidewall insulation patterns; an insulating interlayer covering the conductive patterns, the insulation patterns, the sidewall insulation patterns, and the upper pad patterns; and contact plugs passing through the insulating interlayer, the contact plugs contacting the upper pad patterns, respectively.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: August 16, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jaegoo Lee
  • Patent number: 11417664
    Abstract: A semiconductor device includes a substrate including a first region having a first trench and a second region having a second trench. A first buried insulation layer pattern is disposed in the first trench. The second trench includes the first buried insulation layer pattern, a second buried insulation layer pattern, and a third buried insulation layer pattern sequentially stacked therein. A first buffer insulation layer is disposed on the substrate in the first and second regions and has a flat upper surface. A second buffer insulation layer is disposed on the first buffer insulation layer. A bit line structure is disposed on the first and second regions. A first portion of the bit line structure is disposed on the second buffer insulation layer and has a flat lower surface. A second portion of the bit line structure directly contacts a surface of the substrate in the first region.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: August 16, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jongin Kang
  • Patent number: 11411017
    Abstract: A semiconductor device includes: a stack structure including gate patterns and insulating patterns; a channel layer penetrating the stack structure; a memory layer penetrating the stack structure, the memory layer surrounding the channel layer; and a select transistor connected to the channel layer. The select transistor includes: a carbon layer Schottky-joined with the channel layer; a select gate spaced apart from the carbon layer; and a gate insulating layer between the select gate and the carbon layer.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: August 9, 2022
    Assignee: SK hynix Inc.
    Inventors: Dong Uk Lee, Hae Chang Yang
  • Patent number: 11404550
    Abstract: According to one embodiment, a semiconductor device includes first, and second conductive members, first, second, and third semiconductor regions, and an insulating part. A direction from the first conductive member toward the second conductive member is along a first direction. The first semiconductor region includes first and second partial regions. A second direction from the first partial region toward the second partial region crosses the first direction. The first conductive member is between the first partial region and the second conductive member. A direction from the second partial region toward the second semiconductor region is along the first direction. A direction from the second conductive member toward the second semiconductor region is along the second direction. The third semiconductor region is between the second partial region and the second semiconductor region. The insulating part includes a first insulating region, a second insulating region, and a third insulating region.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: August 2, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoaki Inokuchi, Hiro Gangi, Yusuke Kobayashi, Kentaro Ikeda, Tatsunori Sakano, Ryosuke Iijima
  • Patent number: 11398518
    Abstract: The present technique relates to a solid-state image pickup element and an electronic apparatus each of which enables a pad to be formed in a shallow position while reduction of a quality of a back side illumination type solid-state image pickup element is suppressed. The solid-state image pickup element includes a pixel substrate in which a light condensing layer for condensing incident light on a photoelectric conversion element, a semiconductor layer in which the photoelectric conversion element is formed, and a wiring layer in which a wiring and a pad for outside connection are formed are laminated on one another, and at least a part of a first surface of the pad is exposed through a through hole completely extending through the light condensing layer and the semiconductor layer. The present technique, for example, can be applied to a back side illumination type CMOS image sensor.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: July 26, 2022
    Assignee: SONY CORPORATION
    Inventors: Keishi Inoue, Kenju Nishikido
  • Patent number: 11398477
    Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: July 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jen-Chih Hsueh, Chih-Chang Hung, Tsung Fan Yin, Yi-Wei Chiu