Abstract: A semiconductor device includes a substrate including an active region defined by an isolation layer; a buried gate structure provided in a trench formed in the substrate; and a first doped region and a second doped region formed in the active region and separated by the trench, wherein the buried gate structure includes a gate dielectric layer conformally covering the trench; and a gate electrode including a first portion partially filling the trench on the gate dielectric layer and a second portion formed on the first portion, wherein the second portion includes a material included in the first portion and dopants including phosphorous (P), germanium (Ge), or a combination thereof, and wherein the first portion does not laterally overlap with the doped region and the second doped region, and all or a part of the second portion laterally overlaps with the first doped region and the second doped region.

Abstract: A method for manufacturing the semiconductor structure includes: a substrate is provided; isolation structures having a first depth are formed in the substrate; word line structures having a second depth are formed in the substrate, where part of the word line structures are formed in respective ones of the isolation structures, and the second depth is less than the first depth; the isolation structures are etched in a direction perpendicular to the substrate to form a first trench having a third depth in each isolation structure; and a first insulating layer covering the word line structures and the first trenches is formed on the substrate to form an air gap structure in each isolation structure.

Abstract: A method for evaluating electrical characteristics of a semiconductor substrate, the method including the steps of: forming a p-n junction on a surface of the semiconductor substrate; mounting the semiconductor substrate on a wafer chuck provided with an equipment for performing light irradiation on the surface of the semiconductor substrate and an equipment for measuring the quantity of the light for the irradiation; performing light irradiation on the surface of the semiconductor substrate for a predetermined time; and measuring an amount of carriers generated after the light irradiation of the p-n junction at least after turning off the light irradiation. This provides a method for evaluating a semiconductor substrate that allows the same evaluation in a wafer state as when an actual solid-state image sensor has been formed without producing a device by using process equipment when evaluating characteristics corresponding to residual image characteristics of a wafer.

Abstract: A display device includes a substrate, a plurality of pixels above the substrate, each of the pixels including a light emitting element, a display region including the plurality of pixels, a thin film transistor which each of the plurality of pixels includes, a protective film including a first inorganic insulating material and located between the thin film transistor and the light emitting element, a sealing film including a second inorganic insulating material and covering the light emitting element, and at least one through hole located in the display region and passing through the substrate, the protective film, and the sealing film, wherein the second inorganic insulating material is in direct contact with the protective film in a first region located between the through hole and the pixels.

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers of respective memory cells and control gates, the tier located one over another over a substrate, the control gates including a control gate closest to the substrate, the control gates including respective portions forming a staircase structure; conductive contacts contacting the control gates at a location of the staircase structure, the conductive contacts including a conductive contact contacting the control gate; a dielectric structure located on sidewalls of the control gates; and support structures adjacent the conductive contacts and having lengths extending vertically from the substrate, the support structures including a support structure closest to the conductive contact, the support structure located at a distance from an edge of the dielectric structure, wherein a ratio of a width of the support structure over the distance is ranging from 1.6 to 2.0.

Abstract: A method of manufacturing a superjunction silicon carbide semiconductor device is provided, enabling a reduction of the number of times a combination of epitaxial growth and ion implantation for forming a parallel pn structure is performed. In the method of manufacturing the superjunction silicon carbide semiconductor device, forming an epitaxial layer 2a, 2b of a second conductivity type on a front surface of a silicon carbide semiconductor substrate 1 of a first conductivity type and selectively forming semiconductor regions 4a, 4b of the first conductivity type by implanting nitrogen ions in the epitaxial layer are repeated multiple times, thereby forming the parallel pn structure.

Abstract: Embodiments of the present application disclose a semiconductor structure, a formation method thereof and a memory. The semiconductor structure includes: a substrate; a channel located in the substrate, the channel being configured to form a gate structure; and a convex portion arranged on an inner wall of the channel. The embodiments of the present application can increase a channel length and solve a short-channel effect.

Abstract: A preparation method for a semiconductor device includes: providing a semiconductor substrate, the semiconductor substrate having shallow trenches and active regions defined by the shallow trenches, the active regions extending in a first direction; forming isolation layers in the first direction at interfaces between the shallow trenches and the active regions, the isolation layers and the active regions being inverse types to each other; forming shallow trench isolation structures in the shallow trenches; and forming word-line structures, the word-line structures extending in a second direction and sequentially passing through the shallow trench isolation structures and the active regions.

Abstract: A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: A semiconductor device, including: a transistor layer, including a first active region configured to be a source/drain terminal of a first transistor and a second active region configured to be a source/drain terminal of a second transistor; a dielectric layer, disposed on the source/drain terminals of the first and second transistors; a conductive strip, included in the dielectric layer and extending from the first active region toward the second active region for signal connection.

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.

Abstract: An imprint method includes the following steps. A first resist layer is formed on a first substrate. A first imprinting step using a first mold is performed to the first resist layer. A first etching process is performed to the first substrate with the first resist layer as an etching mask after the first imprinting step so as to form a first recess pattern in the first substrate. A second resist layer is formed on the first substrate. A second imprinting step using a second mold is performed to the second resist layer. A second etching process is performed to the first substrate with the second resist layer as an etching mask after the second imprinting step so as to form second recess patterns in the first substrate. A depth of the first recess pattern is greater than a depth of each of the second recess patterns.

Abstract: Fabrication methods and gallium nitride transistors, in which an electronic device includes a substrate, a buffer structure, a hetero-epitaxy structure over the buffer structure, and a transistor over or in the hetero-epitaxy structure. In one example, the buffer structure has an extrinsically carbon doped gallium nitride layer over a dual superlattice stack or over a multilayer composition graded aluminum gallium nitride stack, and a silicon nitride cap layer over the hetero-epitaxy structure.

Abstract: Using the first robot, the carrier standing by in the load lock chamber is deposited into the reaction chamber without mounting the wafer before processing, and cleaning gas is supplied while the reaction chamber is maintained at a predetermined cleaning temperature, and the carrier that has been cleaned in the reaction chamber is transferred to the load lock chamber using the first robot. The carrier and susceptor are cleaned at a predetermined frequency. After that, the carrier is carried out from the reaction chamber, and the reaction gas is supplied to the reaction chamber to form a polysilicon film on the surface of the susceptor.

Abstract: A display apparatus includes a base layer including device counterparts and bridges, the bridges being located around the device counterparts and connecting the device counterparts to each other, an inorganic insulating layer located over the base layer and having openings exposing at least a portion of at least one of the bridges, organic layers filling the openings, wires located over the organic layers, display devices located over the device counterparts, and encapsulation films each of which has a form of an island to correspond to a corresponding one of the device counterparts, each of the encapsulation films including a first inorganic encapsulation film covering a corresponding one of the display devices, an organic encapsulation film located over the first inorganic encapsulation film, and a second inorganic encapsulation film covering the organic encapsulation film and contacting the first inorganic encapsulation film outside of the organic encapsulation film.

Abstract: According to one embodiment, a semiconductor memory device includes a staircase portion, a columnar body, and a contact. The columnar body is provided in a second region of a stacked body, penetrating the stacked body in a stacking direction, and having a plurality of memory cells at each positions facing the plurality of conductive layers. The contact is connected to a terrace surface. Further, the staircases included in the staircase portion are each formed to ascend for each first step having conductive layers of the plurality of conductive layers in a second direction intersecting the stacking direction and a first direction. The terrace surfaces arranged in the first direction of the terrace surfaces of the staircases are different in height from each other and are formed to ascend for each second step having one conductive layer of the plurality of conductive layers in the first direction.

Abstract: The current disclosure generally relates to the manufacture of semiconductor devices. Specifically, the disclosure relates to methods of depositing a layer on a substrate comprising a recess. The method comprises providing the substrate comprising a recess in a reaction chamber, depositing inhibition material on the substrate to fill the recess with inhibition material, removing the inhibition material from the substrate for exposing a deposition area and depositing a layer on the deposition area by a vapor deposition process. A vapor deposition assembly for performing the method is also disclosed.

Abstract: A method for processing a substrate that includes: loading the substrate in a plasma processing chamber; performing a cyclic plasma etch process including a plurality of cycles, where each cycle of the plurality of cycles includes: generating a first plasma from a first gas mixture including a fluorosilane and oxygen; performing a deposition step by exposing the substrate to the first plasma to form a passivation film including silicon and fluorine; generating a second plasma from a second gas mixture including a noble gas; and performing an etch step by exposing the substrate to the second plasma.

Abstract: A method of microfabrication includes epitaxially growing a first vertical channel structure of silicon-containing material on a first sacrificial layer of silicon containing material, the first sacrificial layer having etch selectivity with respect to the vertical channel structure. A core opening is directionally etched through the vertical channel structure to expose the first sacrificial layer, and the first sacrificial layer is isotropically etched through the core opening to form a first isolation opening for isolating the first vertical channel structure.

Abstract: A semiconductor device includes a pattern structure; a stack structure including gate layers stacked in a first region on the pattern structure and extending into a second region; a memory vertical structure penetrating the stack structure in the first region; gate contact plugs electrically connected to the gate layers in the second region; and a first peripheral contact plug spaced apart from the gate layers, the gate layers including a first gate layer, the gate contact plugs including a first gate contact plug electrically connected to the first gate layer, side surfaces of the first gate contact plug and the first peripheral contact plug having different numbers of upper bending portions, and the number of upper bending portions of the side surface of the first gate contact plug being greater than the number of upper bending portions of the side surface of the first peripheral contact plug.