Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.

Abstract: A semiconductor device, including: a transistor layer, including a first active region configured to be a source/drain terminal of a first transistor and a second active region configured to be a source/drain terminal of a second transistor; a dielectric layer, disposed on the source/drain terminals of the first and second transistors; a conductive strip, included in the dielectric layer and extending from the first active region toward the second active region for signal connection.

Abstract: Using the first robot, the carrier standing by in the load lock chamber is deposited into the reaction chamber without mounting the wafer before processing, and cleaning gas is supplied while the reaction chamber is maintained at a predetermined cleaning temperature, and the carrier that has been cleaned in the reaction chamber is transferred to the load lock chamber using the first robot. The carrier and susceptor are cleaned at a predetermined frequency. After that, the carrier is carried out from the reaction chamber, and the reaction gas is supplied to the reaction chamber to form a polysilicon film on the surface of the susceptor.

Abstract: An imprint method includes the following steps. A first resist layer is formed on a first substrate. A first imprinting step using a first mold is performed to the first resist layer. A first etching process is performed to the first substrate with the first resist layer as an etching mask after the first imprinting step so as to form a first recess pattern in the first substrate. A second resist layer is formed on the first substrate. A second imprinting step using a second mold is performed to the second resist layer. A second etching process is performed to the first substrate with the second resist layer as an etching mask after the second imprinting step so as to form second recess patterns in the first substrate. A depth of the first recess pattern is greater than a depth of each of the second recess patterns.

Abstract: Fabrication methods and gallium nitride transistors, in which an electronic device includes a substrate, a buffer structure, a hetero-epitaxy structure over the buffer structure, and a transistor over or in the hetero-epitaxy structure. In one example, the buffer structure has an extrinsically carbon doped gallium nitride layer over a dual superlattice stack or over a multilayer composition graded aluminum gallium nitride stack, and a silicon nitride cap layer over the hetero-epitaxy structure.

Abstract: A display apparatus includes a base layer including device counterparts and bridges, the bridges being located around the device counterparts and connecting the device counterparts to each other, an inorganic insulating layer located over the base layer and having openings exposing at least a portion of at least one of the bridges, organic layers filling the openings, wires located over the organic layers, display devices located over the device counterparts, and encapsulation films each of which has a form of an island to correspond to a corresponding one of the device counterparts, each of the encapsulation films including a first inorganic encapsulation film covering a corresponding one of the display devices, an organic encapsulation film located over the first inorganic encapsulation film, and a second inorganic encapsulation film covering the organic encapsulation film and contacting the first inorganic encapsulation film outside of the organic encapsulation film.

Abstract: According to one embodiment, a semiconductor memory device includes a staircase portion, a columnar body, and a contact. The columnar body is provided in a second region of a stacked body, penetrating the stacked body in a stacking direction, and having a plurality of memory cells at each positions facing the plurality of conductive layers. The contact is connected to a terrace surface. Further, the staircases included in the staircase portion are each formed to ascend for each first step having conductive layers of the plurality of conductive layers in a second direction intersecting the stacking direction and a first direction. The terrace surfaces arranged in the first direction of the terrace surfaces of the staircases are different in height from each other and are formed to ascend for each second step having one conductive layer of the plurality of conductive layers in the first direction.

Abstract: The current disclosure generally relates to the manufacture of semiconductor devices. Specifically, the disclosure relates to methods of depositing a layer on a substrate comprising a recess. The method comprises providing the substrate comprising a recess in a reaction chamber, depositing inhibition material on the substrate to fill the recess with inhibition material, removing the inhibition material from the substrate for exposing a deposition area and depositing a layer on the deposition area by a vapor deposition process. A vapor deposition assembly for performing the method is also disclosed.

Abstract: A method for processing a substrate that includes: loading the substrate in a plasma processing chamber; performing a cyclic plasma etch process including a plurality of cycles, where each cycle of the plurality of cycles includes: generating a first plasma from a first gas mixture including a fluorosilane and oxygen; performing a deposition step by exposing the substrate to the first plasma to form a passivation film including silicon and fluorine; generating a second plasma from a second gas mixture including a noble gas; and performing an etch step by exposing the substrate to the second plasma.

Abstract: A method of microfabrication includes epitaxially growing a first vertical channel structure of silicon-containing material on a first sacrificial layer of silicon containing material, the first sacrificial layer having etch selectivity with respect to the vertical channel structure. A core opening is directionally etched through the vertical channel structure to expose the first sacrificial layer, and the first sacrificial layer is isotropically etched through the core opening to form a first isolation opening for isolating the first vertical channel structure.

Abstract: A semiconductor device includes a pattern structure; a stack structure including gate layers stacked in a first region on the pattern structure and extending into a second region; a memory vertical structure penetrating the stack structure in the first region; gate contact plugs electrically connected to the gate layers in the second region; and a first peripheral contact plug spaced apart from the gate layers, the gate layers including a first gate layer, the gate contact plugs including a first gate contact plug electrically connected to the first gate layer, side surfaces of the first gate contact plug and the first peripheral contact plug having different numbers of upper bending portions, and the number of upper bending portions of the side surface of the first gate contact plug being greater than the number of upper bending portions of the side surface of the first peripheral contact plug.

Abstract: Method of forming low-k films with reduced dielectric constant, reduced CHx content, and increased hardness are described. A siloxane film is on a substrate surface using a siloxane precursor comprising O—Si—O bonds and cured using ultraviolet light.

Abstract: A cleaning process for cleaning a surface of a semiconductor structure is provided, in which residue layer is formed on the surface of the semiconductor structure. The cleaning process includes providing a first reaction gas and a second reaction gas to the surface of the semiconductor structure, in which the first reaction gas reacts with the second reaction gas to remove the residue layer while forming a protection layer on the surface of the semiconductor structure.

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

Abstract: A semiconductor device includes first and second gate structures respectively on first and second active regions and an insulating layer between the first and second active regions and a separation structure between a first end portion of the first gate structure and a second end portion of the second gate structure and extending into the insulating layer. The separation structure includes a lower portion, an intermediate portion, and an upper portion, a maximum width of the intermediate portion in the first direction is greater than a maximum width of the lower portion in the first direction, and the maximum width of the intermediate portion is greater than a maximum width of the upper portion in the first direction.

Abstract: The present invention relates to the field of semiconductor manufacturing technologies, in particular to a semiconductor device and a method of forming the same. The method of forming the semiconductor device includes the following steps: forming a substrate with a trench, a gate dielectric layer covering an inner wall of the trench, a barrier layer covering a portion of a surface of the gate dielectric layer, and a first gate layer filled on an surface of the barrier layer being disposed in the trench; removing a portion of the barrier layer to form an groove located between the first gate layer and the gate dielectric layer; forming a channel dielectric layer at least covering an inner wall of the groove and a top surface of the first gate layer; and forming a second gate layer at least partially filling an interior of the groove.

Abstract: An apparatus for processing a substrate may comprise a reaction chamber, a substrate support disposed within the reaction chamber and provided with a support surface to support the substrate, and a motor to provide a rotary movement, wherein the motor is controlled and configured to create a bidirectional rotary movement between the reaction chamber and the substrate support around an axis perpendicular to the support surface.

Abstract: A method of processing a substrate that includes: depositing a photoactive metal-based hard mask (photo-MHM) over an underlying layer, the underlying layer formed over a substrate, the photo-MHM including a metal; depositing a dielectric over the photo-MHM; etching a portion of the dielectric to form a first feature; depositing a spacer material over the first feature; etching the spacer material to expose top surfaces of the dielectric and a first portion of the photo-MHM; exposing the photo-MHM to a first ultraviolet light (UV) radiation through a first photomask, a first unmasked region of the photo-MHM being photoreacted due to the exposure to the first UV radiation; after the exposure, developing the photo-MHM to form a second feature in the photo-MHM; and etching the underlying layer using the photo-MHM as an etch mask.

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.

Abstract: Disclosed herein are colored gratings in microelectronic structures. For example, a microelectronic structure may include first conductive structures alternating with second conductive structures, wherein individual ones of the first conductive structures include a bottom portion and a top portion, individual cap structures are on individual ones of the second conductive structures, the bottom portions of the first conductive structures are laterally spaced apart from and aligned with the second conductive structures, and the top portions of the first conductive structures are laterally spaced apart from and aligned with the cap structures. In some embodiments, a microelectronic structure may include one or more unordered lamellar regions laterally spaced apart from and aligned with the first conductive structures.