Abstract: A vapor deposition mask made of metal includes: a front surface configured to oppose a vapor deposition source; and mask holes each including a hole portion having a shape of an inverted frustum. The hole portion of each of the mask holes includes: a small opening including a polygonal edge as seen from a view opposing the front surface of the vapor deposition mask, the edge including corners and linear portions each located between adjacent ones of the corners; and a large opening located on the front surface, the large opening including an edge as seen from the view opposing the front surface of the vapor deposition mask, the edge being shaped such that the corners of the edge of the small opening project outward from the edge of the small opening. The large opening surrounds the small opening as seen from the view opposing the front surface.

Abstract: A method of fabricating a semiconductor device includes providing a wafer inside a process chamber, performing an ALD (atomic layer deposition) process inside the process chamber to deposit titanium nitride on the wafer, providing a process gas used for the ALD process to a scrubber, filtering a first powder contained in the process gas, using a filter unit disposed in the scrubber and including a plurality of filters, adsorbing a second powder remaining in the process gas after passing through the filter unit, using a fin structure extending in a vertical direction inside the filter unit, and exhausting the process gas, from which the first and second powders are removed, from the scrubber.

Abstract: A technique for improving uniformity of film thickness on substrates, includes a substrate processing apparatus having a substrate retainer including substrate and partition plate supports; a reaction tube; a first driver vertically moving the substrate retainer into or out of the reaction tube; a second driver vertically moved by the first driver and rotating the substrate retainer to change a distance between a substrate and a partition plate by moving at least one of the substrate or the partition plate support; a heater; a gas supplier comprising a nozzle; a gas exhauster; and a controller controlling the first driver, the second driver and the gas supplier such that a gas is supplied to the substrate while changing at least one of a relative position of the substrate and a relative position of the partition plate with respect to a hole of the nozzle by driving the second driver.

Abstract: Threshold voltage (Vt) tuning layers may be sensitive to etching by reactants used to deposit overlying gate material, such as metal nitride. Methods for depositing Vt tuning layers are provided. In some embodiments Vt tuning layers may comprise a Vt tuning material in a neutral matrix. In some embodiments, processes for reducing or eliminating the etching of Vt tuning layers by halide reactants are described. In some embodiments a Vt tuning layer, such as a metal oxide layer, is treated by a nitridation process following deposition and prior to subsequent deposition of a metal nitride capping layer. In some embodiments an etch-protective layer, such as a NbO layer, is deposited over a Vt tuning layer prior to deposition of an overlying metal nitride layer.

Abstract: The present invention disclosures a critical dimension error analysis method, comprising: S01: performing lithography processes on a wafer, measuring the critical dimension (CD) values of the test points in each of the fields respectively; M and N are integers greater than 1; S02: removing extreme outliers from the critical dimension (CD) values; S03: rebuilding remaining CD values by a reconstruction model fitting method, and obtaining rebuilt critical dimension (CD?) values, according to relative error between CD? and CD, dividing the rebuilt critical dimension (CD?) values into scenes and the number of the scenes is A; S04: calculating components and corresponding residuals of the test points in each of the scenes under a reference system corresponding to a correction model by parameter estimation; S05: modifying machine parameters and masks by the correction model according to above calculation results.

Abstract: The present disclosure provide a semiconductor device and a method for preparing the semiconductor device. The semiconductor device includes a first buried gate structure and a second buried gate structure disposed in a semiconductor substrate. The first buried gate structure includes a first gate dielectric layer, and a first lower semiconductor layer disposed over the first gate dielectric layer. The first lower semiconductor layer has a T-shaped profile in a cross-sectional view. The first buried gate structure also includes a first upper semiconductor layer disposed over the first lower semiconductor layer. The second buried gate structure includes a second gate dielectric layer, and a second lower semiconductor layer disposed over the second gate dielectric layer. The second lower semiconductor layer has a U-shaped profile in the cross-sectional view. The second buried gate structure also includes a second upper semiconductor layer disposed over the second lower semiconductor layer.

Abstract: A method of deposition on a substrate used for the manufacture of a solar cell is provided. The method includes depositing a first conductive pattern on a first side of the substrate. The first conductive pattern is one of a plurality of busbars and a plurality of fingers. The method includes providing a screen over the substrate. The screen includes a set of openings. The screen has a bottom side having a varying vertical profile including low portions and high portions. The method includes transferring a printing material from the screen to the substrate through the set of openings to print a second conductive pattern on the first side of the substrate. The second conductive pattern is the other one of the plurality of busbars and the plurality of fingers. During the printing of the second conductive pattern, the first conductive pattern is substantially wet and the screen is disposed over the substrate in a manner such that the high portions are elevated above the first conductive pattern.

Abstract: A method of detecting defects on a semiconductor wafer includes directing diffuse light to the semiconductor wafer and reflecting the diffuse light off of the semiconductor wafer. The method further includes detecting the diffuse light with a camera to generate an image of the semiconductor wafer and analyzing the image to detect defects on the semiconductor wafer.

Abstract: A method for reducing bending of word lines in a memory cell includes a) providing a substrate including a plurality of word lines arranged adjacent to one another and above a plurality of transistors; b) depositing a layer of film on the plurality of word lines using a deposition process; c) after depositing the layer of film, measuring word line bending; d) comparing the word line bending to a predetermined range; e) based on the word line bending, adjusting at least one of nucleation delay and grain size of the deposition process; and f) repeating b) to e) one or more times using one or more substrates, respectively, until the word line bending is within the predetermined range.

Abstract: A semiconductor device with a passing gate is provided. The semiconductor device includes a substrate having a first trench and a first gate structure in the first trench. The first gate structure includes a first gate electrode having a first doped region.

Abstract: A superlattice cell that includes Group IV elements is repeated multiple times so as to form the superlattice. Each superlattice cell has multiple ordered atomic planes that are parallel to one another. At least two of the atomic planes in the superlattice cell have different chemical compositions. One or more of the atomic planes in the superlattice cell one or more components selected from the group consisting of carbon, tin, and lead. These superlattices make a variety of applications including, but not limited to, transistors, light sensors, and light sources.

Abstract: A high aspect ratio contact structure formed within a dielectric material includes a top portion and a bottom portion. The top portion of the contact structure includes a tapering profile towards the bottom portion. A first metal stack surrounded by an inner spacer is located within the top portion of the contact structure and a second metal stack is located within the bottom portion of the contact structure. A width of the bottom portion of the contact structure is greater than a minimum width of the top portion of the contact structure.

Abstract: A method of forming a microelectronic device including a first stack structure comprising alternating levels of insulative structures and other insulative structures, forming strings of memory cells through the first stack structure, forming a second stack structure over the first stack structure, based at least partially on observed amount of pillar bending within the first stack structure, forming a first tailored reticle specific to the observed amount of pillar bending, utilizing the first tailored reticle to form openings extending through the second stack structure and over some of the strings of memory cells, wherein centers of the openings over the strings of memory cells are at least substantially aligned with the centers of uppermost surfaces of the strings of memory cells in a direction of the observed pillar bending, and forming upper pillars extending through the second stack structure and over some of the strings of memory cells.

Abstract: An electronic component transfer apparatus is configured to transfer an electronic component on a flexible carrier to a target substrate. The electronic component transfer apparatus includes a first frame, a second frame, an abutting component, an actuating mechanism, an energy generating device, an image capture device, and a data processing module. The first frame is configured to carry the flexible carrier. The second frame is configured to carry the target substrate. The abutting component is disposed adjacent to the flexible carrier. The actuating mechanism is configured to actuate the abutting component, so that the abutting end of the abutting component abuts against the flexible carrier. The energy generating device generates an energy beam. The image capture device captures an image through the abutting component. The data processing module receives and computes the image to determine whether to adjust the relative position between the abutting end and the flexible carrier.

Abstract: A semiconductor device includes a semiconductor substrate, a word line trench and a word line structure. The word line trench includes a first word line trench and a second word line trench. The word line structure includes a first word line structure part and a second word line structure part connected to each other. The first word line structure part is formed in the first word line trench, and the second word line structure part is formed in the second word line trench; and the first word line structure part includes an avoidance region, and the top surface of the avoidance region is aligned with the top surface of the second word line structure part, and the avoidance region is provided with insulating material.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a semiconductor substrate, a trench, and a word line structure in the trench. The semiconductor substrate has a first active region and an isolation layer. The first active region includes a first sub-active region, a second sub-active region, and a first separation channel separating the first sub-active region from the second sub-active region. The word line structure is adjacent to the first active region and includes a word line insulating layer covering inner side surfaces of the trench, a word line electrode on the word line insulating layer, and a word line capping structure on the word line electrode. A depth of the first separation channel is substantially identical to a thickness of the isolation layer.

Abstract: A method is provided. A substrate situated in a chamber is exposed to a halogen-containing gas comprising an element selected from the group consisting of silicon, germanium, carbon, titanium, and tin, and igniting a plasma to modify a surface of the substrate and form a modified surface. The substrate is exposed to an activated activation gas to etch at least part of the modified surface.

Abstract: A cell on an integrated circuit is provided. The cell includes: a fin structure; an intermediate fin structure connection metal track disposed in an intermediate fin structure connection metal layer above the fin structure, the intermediate fin structure connection metal track being connected to the fin structure; and a first intermediate gate connection metal track disposed in an intermediate gate connection metal layer above the intermediate fin structure connection metal layer, the first intermediate gate connection metal track being connected to the intermediate fin structure connection metal track. A first power supply terminal is connected to the first intermediate gate connection metal track.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a semiconductor substrate, a trench, and a word line structure in the trench. The semiconductor substrate has a first active region and an isolation layer. The first active region includes a first sub-active region, a second sub-active region, and a first separation channel separating the first sub-active region from the second sub-active region. The word line structure is adjacent to the first active region and includes a word line insulating layer covering inner side surfaces of the trench, a word line electrode on the word line insulating layer, and a word line capping structure on the word line electrode. A depth of the first separation channel is substantially identical to a thickness of the isolation layer.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a substrate; forming a conductive layer on the substrate; patterning the conductive layer to form a first metallization layer and a second metallization layer extending along a first direction, wherein the first metallization layer has a first protruding portion protruding toward the second metallization layer; and forming a first channel layer within the first metallization layer and a second channel layer within the second metallization layer.