Abstract: A semiconductor device includes a semiconductor substrate, a word line trench and a word line structure. The word line trench includes a first word line trench and a second word line trench. The word line structure includes a first word line structure part and a second word line structure part connected to each other. The first word line structure part is formed in the first word line trench, and the second word line structure part is formed in the second word line trench; and the first word line structure part includes an avoidance region, and the top surface of the avoidance region is aligned with the top surface of the second word line structure part, and the avoidance region is provided with insulating material.

Abstract: An electronic component transfer apparatus is configured to transfer an electronic component on a flexible carrier to a target substrate. The electronic component transfer apparatus includes a first frame, a second frame, an abutting component, an actuating mechanism, an energy generating device, an image capture device, and a data processing module. The first frame is configured to carry the flexible carrier. The second frame is configured to carry the target substrate. The abutting component is disposed adjacent to the flexible carrier. The actuating mechanism is configured to actuate the abutting component, so that the abutting end of the abutting component abuts against the flexible carrier. The energy generating device generates an energy beam. The image capture device captures an image through the abutting component. The data processing module receives and computes the image to determine whether to adjust the relative position between the abutting end and the flexible carrier.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a semiconductor substrate, a trench, and a word line structure in the trench. The semiconductor substrate has a first active region and an isolation layer. The first active region includes a first sub-active region, a second sub-active region, and a first separation channel separating the first sub-active region from the second sub-active region. The word line structure is adjacent to the first active region and includes a word line insulating layer covering inner side surfaces of the trench, a word line electrode on the word line insulating layer, and a word line capping structure on the word line electrode. A depth of the first separation channel is substantially identical to a thickness of the isolation layer.

Abstract: A method is provided. A substrate situated in a chamber is exposed to a halogen-containing gas comprising an element selected from the group consisting of silicon, germanium, carbon, titanium, and tin, and igniting a plasma to modify a surface of the substrate and form a modified surface. The substrate is exposed to an activated activation gas to etch at least part of the modified surface.

Abstract: A cell on an integrated circuit is provided. The cell includes: a fin structure; an intermediate fin structure connection metal track disposed in an intermediate fin structure connection metal layer above the fin structure, the intermediate fin structure connection metal track being connected to the fin structure; and a first intermediate gate connection metal track disposed in an intermediate gate connection metal layer above the intermediate fin structure connection metal layer, the first intermediate gate connection metal track being connected to the intermediate fin structure connection metal track. A first power supply terminal is connected to the first intermediate gate connection metal track.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a semiconductor substrate, a trench, and a word line structure in the trench. The semiconductor substrate has a first active region and an isolation layer. The first active region includes a first sub-active region, a second sub-active region, and a first separation channel separating the first sub-active region from the second sub-active region. The word line structure is adjacent to the first active region and includes a word line insulating layer covering inner side surfaces of the trench, a word line electrode on the word line insulating layer, and a word line capping structure on the word line electrode. A depth of the first separation channel is substantially identical to a thickness of the isolation layer.

Abstract: Disclosed is a method for stripping a gallium nitride substrate, including: a gallium nitride substrate with a gallium nitride epitaxial structure directly grown on an upper surface thereof is acquired; an interior of the gallium nitride substrate is scanned and irradiated via the epitaxial structure by a laser beam, so as to generate a decomposition layer in the gallium nitride substrate, the laser beam being a laser having a pulse width on the order of less than 10?15 s, and a distance between the decomposition layer and the upper surface of the gallium nitride substrate being less than a thickness of the gallium nitride substrate; and the gallium nitride substrate is separated at the decomposition layer, so as to obtain a stripped gallium nitride substrate and a semiconductor device.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a substrate; forming a conductive layer on the substrate; patterning the conductive layer to form a first metallization layer and a second metallization layer extending along a first direction, wherein the first metallization layer has a first protruding portion protruding toward the second metallization layer; and forming a first channel layer within the first metallization layer and a second channel layer within the second metallization layer.

Abstract: Active protection circuits for semiconductor devices, and associated systems and methods, are disclosed herein. The active protection circuits may protect various components of the semiconductor devices from process induced damage—e.g., stemming from process charging effects. In some embodiments, the active protection circuit includes an FET and a resistor coupled to certain nodes (e.g., source plates for 3D NAND memory arrays) of the semiconductor devices, which may be prone to accumulate the process charging effects. The active protection circuits prevent the nodes from reaching a predetermined voltage during process steps utilizing charged particles. Subsequently, metal jumpers may be added to the active protection circuits to deactivate the FETs for normal operations of the semiconductor devices. Further, the FET and the resistor of the active protection circuit may be integrated with an existing component of the semiconductor device.

Abstract: Semiconductor devices and methods are provided which facilitate performing physical failure analysis (PFA) testing from a backside of the devices. In at least one example, a device is provided that includes a semiconductor device layer including a plurality of diffusion regions. A first interconnection structure is disposed on a first side of the semiconductor device layer, and the first interconnection structure includes at least one electrical contact. A second interconnection structure is disposed on a second side of the semiconductor device layer, and the second interconnection structure includes a plurality of backside power rails. Each of the backside power rails at least partially overlaps a respective diffusion region of the plurality of diffusion regions and defines openings which expose portions of the respective diffusion region at the second side of the semiconductor device layer.

Abstract: A 3D memory array includes a row of stacks, each stack having alternating gate strips and dielectric strips. Dielectric plugs are disposed between the stacks and define cell areas. A data storage film and a channel film are disposed adjacent the stacks on the sides of the cell areas. The middles of the cell areas are filled with an intracell dielectric. Source lines and drain lines form vias through the intracell dielectric. The source lines and the drain lines are each provided with a bulge toward the interior of the cell area. The bulges increase the areas of the source line and the drain line without reducing the channel lengths. In some of these teachings, the areas of the source lines and the drain lines are increased by restricting the data storage film or the channel layer to the sides of the cell areas adjacent the stacks.

Abstract: A method for depositing a silicon nitride layer on a stack is provided. The method comprises providing an atomic layer deposition, comprising a plurality of cycles, wherein each cycle comprises dosing the stack with a silicon containing precursor by providing a silicon containing precursor gas, providing an N2 plasma conversion, and providing an H2 plasma conversion.

Abstract: A substrate processing method capable of stably loading a substrate regardless of a variation in pressure of a reaction space includes supplying an inert gas; and forming a thin film by sequentially and repeatedly supplying a source gas, supplying a reaction gas, and activating the reaction gas, wherein a center portion of a substrate and a center portion of a susceptor are spaced apart from each other to form a separate space, the reaction space above the substrate and the separate space communicate with each other via one or more channels, an inert gas is introduced to the separate space through the one or more channels during the supplying of the inert gas, and the inert gas prevents pressure imbalance between the separate space and the reaction space during a thin film deposition process.

Abstract: A stirrer includes a magnetic bar and a microwave absorbing layer around the magnetic bar. The stirrer absorbs a microwave and converts the microwave to thermal energy to heat the mixed solution reactant.

Abstract: A manufacturing method of a semiconductor device includes forming a stack of first semiconductor layers and second semiconductor layers alternatively formed on top of one another, where a topmost layer of the stack is one of the second semiconductor layers; forming a patterned mask layer on the topmost layer of the stack; forming a trench in the stack based on the patterned mask layer to form a fin structure; forming a cladding layer extending along sidewalls of the fin structure; and removing the patterned mask layer and a portion of the cladding layer by performing a two-step etching process, where the portion of the cladding layer is removed to form cladding spacers having a concave top surface with a recess depth increasing from the sidewalls of the fin structure.

Abstract: A semiconductor device includes a substrate, first word lines and second word lines; one or more first word line trenches and one or more second word line trenches are alternately arranged on the substrate in parallel; each first word line is arranged in a respective first word line trench; each second word line is arranged in a respective second word line trench, where width of the first word line trench is greater than width of the second word line trench, and depth of the first word line trench is less than depth of the second word line trench, so that width of the first word line is greater than width of the second word line, height of the first word line is less than height of the second word line, and threshold voltage of the first word line is greater than threshold voltage of the second word line.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a plurality of nanowire structures over a channel region of a semiconductor fin structure, a source/drain feature on a source/drain region of the semiconductor fin structure, and a dielectric fin structure spaced apart from the source/drain feature and the semiconductor fin structure. A top surface of the dielectric fin structure is higher than a top surface of a bottommost one of the nanowire structures, and a bottom surface of the dielectric fin structure is lower than a bottom surface of the source/drain feature.

Abstract: Embodiments of the present application relate to the field of semiconductors, and provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, including active regions arranged at intervals and an isolation structure located between the active regions; a word line (WL) trench, penetrating through the active region and the isolation structure along a first direction; and a WL, located in the WL trench, wherein on a section in a second direction, a first height difference is formed between the active region and the isolation structure; and the second direction is parallel to the substrate and perpendicular to the first direction.

Abstract: A method of making an acoustic sensor (e.g., for use in a piezoelectric MEMS microphone) includes forming or providing a mold having one or more grooves in a top surface of the mold that extend in a direction of the length of the mold to a distal end of the mold. The method also includes forming or depositing a structure having one or more piezoelectric layers over the top surface of the mold to define a beam, the distal portion of the beam having a corrugated section including one or more grooves that correspond to the grooves of the mold. The method also includes forming a gap in the structure to define two beams separated by the gap, and releasing the structure from the mold to form one or more cantilever beams that increases an acoustic resistance of the gap between sensors.

Abstract: A high-speed layout device for a photovoltaic module includes a module input unit, a module output unit, a tray transfer unit, and a layout transfer unit. The tray transfer unit extends into a position below the module input unit to lift the photovoltaic module, moves horizontally, places the photovoltaic module on the module output unit for outputting, and then returns to the position below the module input unit. A layout of a middle row of battery strings is performed on the tray transfer unit, a layout of a first row of battery strings is performed on the input unit or the tray transfer unit, and a layout of a last row of battery strings is performed on the tray transfer unit or the output unit, wherein the layout of the first row of battery strings and the layout of the last row of battery strings are performed on different units.