Abstract: The present disclosure provide a semiconductor device and a method for preparing the semiconductor device. The semiconductor device includes a first buried gate structure and a second buried gate structure disposed in a semiconductor substrate. The first buried gate structure includes a first gate dielectric layer, and a first lower semiconductor layer disposed over the first gate dielectric layer. The first lower semiconductor layer has a T-shaped profile in a cross-sectional view. The first buried gate structure also includes a first upper semiconductor layer disposed over the first lower semiconductor layer. The second buried gate structure includes a second gate dielectric layer, and a second lower semiconductor layer disposed over the second gate dielectric layer. The second lower semiconductor layer has a U-shaped profile in the cross-sectional view. The second buried gate structure also includes a second upper semiconductor layer disposed over the second lower semiconductor layer.

Abstract: A method of deposition on a substrate used for the manufacture of a solar cell is provided. The method includes depositing a first conductive pattern on a first side of the substrate. The first conductive pattern is one of a plurality of busbars and a plurality of fingers. The method includes providing a screen over the substrate. The screen includes a set of openings. The screen has a bottom side having a varying vertical profile including low portions and high portions. The method includes transferring a printing material from the screen to the substrate through the set of openings to print a second conductive pattern on the first side of the substrate. The second conductive pattern is the other one of the plurality of busbars and the plurality of fingers. During the printing of the second conductive pattern, the first conductive pattern is substantially wet and the screen is disposed over the substrate in a manner such that the high portions are elevated above the first conductive pattern.

Abstract: A method for reducing bending of word lines in a memory cell includes a) providing a substrate including a plurality of word lines arranged adjacent to one another and above a plurality of transistors; b) depositing a layer of film on the plurality of word lines using a deposition process; c) after depositing the layer of film, measuring word line bending; d) comparing the word line bending to a predetermined range; e) based on the word line bending, adjusting at least one of nucleation delay and grain size of the deposition process; and f) repeating b) to e) one or more times using one or more substrates, respectively, until the word line bending is within the predetermined range.

Abstract: A semiconductor device with a passing gate is provided. The semiconductor device includes a substrate having a first trench and a first gate structure in the first trench. The first gate structure includes a first gate electrode having a first doped region.

Abstract: A method of detecting defects on a semiconductor wafer includes directing diffuse light to the semiconductor wafer and reflecting the diffuse light off of the semiconductor wafer. The method further includes detecting the diffuse light with a camera to generate an image of the semiconductor wafer and analyzing the image to detect defects on the semiconductor wafer.

Abstract: A superlattice cell that includes Group IV elements is repeated multiple times so as to form the superlattice. Each superlattice cell has multiple ordered atomic planes that are parallel to one another. At least two of the atomic planes in the superlattice cell have different chemical compositions. One or more of the atomic planes in the superlattice cell one or more components selected from the group consisting of carbon, tin, and lead. These superlattices make a variety of applications including, but not limited to, transistors, light sensors, and light sources.

Abstract: A method of forming a microelectronic device including a first stack structure comprising alternating levels of insulative structures and other insulative structures, forming strings of memory cells through the first stack structure, forming a second stack structure over the first stack structure, based at least partially on observed amount of pillar bending within the first stack structure, forming a first tailored reticle specific to the observed amount of pillar bending, utilizing the first tailored reticle to form openings extending through the second stack structure and over some of the strings of memory cells, wherein centers of the openings over the strings of memory cells are at least substantially aligned with the centers of uppermost surfaces of the strings of memory cells in a direction of the observed pillar bending, and forming upper pillars extending through the second stack structure and over some of the strings of memory cells.

Abstract: A high aspect ratio contact structure formed within a dielectric material includes a top portion and a bottom portion. The top portion of the contact structure includes a tapering profile towards the bottom portion. A first metal stack surrounded by an inner spacer is located within the top portion of the contact structure and a second metal stack is located within the bottom portion of the contact structure. A width of the bottom portion of the contact structure is greater than a minimum width of the top portion of the contact structure.

Abstract: An electronic component transfer apparatus is configured to transfer an electronic component on a flexible carrier to a target substrate. The electronic component transfer apparatus includes a first frame, a second frame, an abutting component, an actuating mechanism, an energy generating device, an image capture device, and a data processing module. The first frame is configured to carry the flexible carrier. The second frame is configured to carry the target substrate. The abutting component is disposed adjacent to the flexible carrier. The actuating mechanism is configured to actuate the abutting component, so that the abutting end of the abutting component abuts against the flexible carrier. The energy generating device generates an energy beam. The image capture device captures an image through the abutting component. The data processing module receives and computes the image to determine whether to adjust the relative position between the abutting end and the flexible carrier.

Abstract: A semiconductor device includes a semiconductor substrate, a word line trench and a word line structure. The word line trench includes a first word line trench and a second word line trench. The word line structure includes a first word line structure part and a second word line structure part connected to each other. The first word line structure part is formed in the first word line trench, and the second word line structure part is formed in the second word line trench; and the first word line structure part includes an avoidance region, and the top surface of the avoidance region is aligned with the top surface of the second word line structure part, and the avoidance region is provided with insulating material.

Abstract: A cell on an integrated circuit is provided. The cell includes: a fin structure; an intermediate fin structure connection metal track disposed in an intermediate fin structure connection metal layer above the fin structure, the intermediate fin structure connection metal track being connected to the fin structure; and a first intermediate gate connection metal track disposed in an intermediate gate connection metal layer above the intermediate fin structure connection metal layer, the first intermediate gate connection metal track being connected to the intermediate fin structure connection metal track. A first power supply terminal is connected to the first intermediate gate connection metal track.

Abstract: A method is provided. A substrate situated in a chamber is exposed to a halogen-containing gas comprising an element selected from the group consisting of silicon, germanium, carbon, titanium, and tin, and igniting a plasma to modify a surface of the substrate and form a modified surface. The substrate is exposed to an activated activation gas to etch at least part of the modified surface.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a semiconductor substrate, a trench, and a word line structure in the trench. The semiconductor substrate has a first active region and an isolation layer. The first active region includes a first sub-active region, a second sub-active region, and a first separation channel separating the first sub-active region from the second sub-active region. The word line structure is adjacent to the first active region and includes a word line insulating layer covering inner side surfaces of the trench, a word line electrode on the word line insulating layer, and a word line capping structure on the word line electrode. A depth of the first separation channel is substantially identical to a thickness of the isolation layer.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a semiconductor substrate, a trench, and a word line structure in the trench. The semiconductor substrate has a first active region and an isolation layer. The first active region includes a first sub-active region, a second sub-active region, and a first separation channel separating the first sub-active region from the second sub-active region. The word line structure is adjacent to the first active region and includes a word line insulating layer covering inner side surfaces of the trench, a word line electrode on the word line insulating layer, and a word line capping structure on the word line electrode. A depth of the first separation channel is substantially identical to a thickness of the isolation layer.

Abstract: Disclosed is a method for stripping a gallium nitride substrate, including: a gallium nitride substrate with a gallium nitride epitaxial structure directly grown on an upper surface thereof is acquired; an interior of the gallium nitride substrate is scanned and irradiated via the epitaxial structure by a laser beam, so as to generate a decomposition layer in the gallium nitride substrate, the laser beam being a laser having a pulse width on the order of less than 10?15 s, and a distance between the decomposition layer and the upper surface of the gallium nitride substrate being less than a thickness of the gallium nitride substrate; and the gallium nitride substrate is separated at the decomposition layer, so as to obtain a stripped gallium nitride substrate and a semiconductor device.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a substrate; forming a conductive layer on the substrate; patterning the conductive layer to form a first metallization layer and a second metallization layer extending along a first direction, wherein the first metallization layer has a first protruding portion protruding toward the second metallization layer; and forming a first channel layer within the first metallization layer and a second channel layer within the second metallization layer.

Abstract: Semiconductor devices and methods are provided which facilitate performing physical failure analysis (PFA) testing from a backside of the devices. In at least one example, a device is provided that includes a semiconductor device layer including a plurality of diffusion regions. A first interconnection structure is disposed on a first side of the semiconductor device layer, and the first interconnection structure includes at least one electrical contact. A second interconnection structure is disposed on a second side of the semiconductor device layer, and the second interconnection structure includes a plurality of backside power rails. Each of the backside power rails at least partially overlaps a respective diffusion region of the plurality of diffusion regions and defines openings which expose portions of the respective diffusion region at the second side of the semiconductor device layer.

Abstract: Active protection circuits for semiconductor devices, and associated systems and methods, are disclosed herein. The active protection circuits may protect various components of the semiconductor devices from process induced damage—e.g., stemming from process charging effects. In some embodiments, the active protection circuit includes an FET and a resistor coupled to certain nodes (e.g., source plates for 3D NAND memory arrays) of the semiconductor devices, which may be prone to accumulate the process charging effects. The active protection circuits prevent the nodes from reaching a predetermined voltage during process steps utilizing charged particles. Subsequently, metal jumpers may be added to the active protection circuits to deactivate the FETs for normal operations of the semiconductor devices. Further, the FET and the resistor of the active protection circuit may be integrated with an existing component of the semiconductor device.

Abstract: A stirrer includes a magnetic bar and a microwave absorbing layer around the magnetic bar. The stirrer absorbs a microwave and converts the microwave to thermal energy to heat the mixed solution reactant.

Abstract: A method for depositing a silicon nitride layer on a stack is provided. The method comprises providing an atomic layer deposition, comprising a plurality of cycles, wherein each cycle comprises dosing the stack with a silicon containing precursor by providing a silicon containing precursor gas, providing an N2 plasma conversion, and providing an H2 plasma conversion.