Patents Examined by Hsien Ming Lee
  • Patent number: 10388659
    Abstract: A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: August 20, 2019
    Assignee: STMICROELECTRONICS, INC.
    Inventor: John H. Zhang
  • Patent number: 10388212
    Abstract: An organic light emitting diode display includes a substrate. The substrate defines a first pixel portion and one or more second pixel portions. Pixels formed in the first pixel portion include at least some transparent organic light emitting diode pixels, while other pixels formed in the one or more second pixel portions include only reflective organic light emitting diode pixels.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: August 20, 2019
    Assignee: Motorola Mobility LLC
    Inventor: Ye Yang
  • Patent number: 10381315
    Abstract: A hardware-embedded security system is described. The system includes connective components, circuit elements and an insulator. The connective components include a variable conductivity layer that is conductive for a first stoichiometry and insulating for a second stoichiometry. The variable conductivity layer is conductive for a first portion of the connective components connected to a first portion of the circuit elements. The variable conductivity layer is insulating for a second portion of the connective components connected to a second portion of the circuit elements. Thus, the first portion of the circuit elements are active and the second portion of the circuit elements are inactive. The insulator is adjacent to at least a portion of each of the connective components. The first stoichiometry may be indistinguishable from the second stoichiometry via optical imaging and electron imaging of a portion of the insulator and the variable conductivity layer.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: August 13, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Harsono S. Simka, Ganesh Hegde, Joon Goo Hong, Rwik Sengupta, Mark S. Rodder
  • Patent number: 10381339
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a first and second dummy memory cell positioned within a dummy memory bank area. A first dummy top electrode overlies the first and second dummy memory cells, and is in electrical communication with the first and second dummy memory cells. A test circuit is in electrical communication with the first dummy top electrode.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: August 13, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Chenchen Jacob Wang, Teck Leong Wee, Dimitri Houssameddine
  • Patent number: 10374103
    Abstract: A method is presented for integrating an electronic component in back end of the line (BEOL) processing. The method includes forming a first electrode over a semiconductor substrate, forming a first electrically conductive material over a portion of the first electrode, and forming a second electrically conductive material over the first electrically conductive material, where the first and second electrically conductive materials define a p-n junction. The method further includes depositing a second electrode between a set of spacers and in direct contact with the p-n-junction, depositing a phase change material over the p-n junction and in direct contact with the second electrode, and forming a third electrode over a portion of the phase change material.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Fabio Carta, Chung H. Lam, Matthew J. BrightSky, Bahman Hekmatshoartabari
  • Patent number: 10357881
    Abstract: A multi-segment robot for emotive expression includes a first segment having a generally planar surface, a second segment having a first axis of rotation, the second segment in rotational contact with the first segment about the first axis of rotation; and a third segment in rotational contact with the second segment about a second axis of rotation not parallel to the first axis of rotation, the third segment having a display screen adapted to facilitate social interaction with a user.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: July 23, 2019
    Assignee: SQN VENTURE INCOME FUND, L.P.
    Inventors: Fardad Faridi, Cynthia Breazeal
  • Patent number: 10361113
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having an enhanced gap fill layer in trenches. The present disclosure provides a novel gap fill layer formed using a multi-step deposition and in-situ treatment process. The deposition process can be a flowable chemical vapor deposition (FCVD) utilizing one or more assist gases and molecules of low reactive sticking coefficient (RSC). The treatment process can be an in-situ process after the deposition process and includes exposing the deposited gap fill layer to plasma activated assist gas. The assist gas can be formed of ammonia. The low RSC molecule can be formed of trisilylamin (TSA) or perhydropolysilazane (PHPS).
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: July 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jian-Shiou Huang, Bang-Tai Tang, Chih-Tang Peng, Tai-Chun Huang, Yen-Chun Huang
  • Patent number: 10354953
    Abstract: There is provided a semiconductor device including a memory region and a logic region. The memory region includes a transistor (memory transistor) that stores information by accumulating charge in a sidewall insulating film. The width of the sidewall insulating film of the memory transistor included in the memory region is made larger than the width of a sidewall insulating film of a transistor (logic transistor) included in the logic region.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: July 16, 2019
    Assignee: MIE FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji Ema, Makoto Yasuda, Kazuhiro Mizutani
  • Patent number: 10354864
    Abstract: A compound semiconductor substrate having a desired quality is provided. A compound semiconductor substrate has an SiC (silicon carbide) layer, an AlN (aluminum nitride) buffer layer formed on the SiC layer, an Al (aluminum) nitride semiconductor layer formed on the AlN buffer layer, a first GaN (gallium nitride) layer formed on the Al nitride semiconductor layer, a first AlN intermediate layer formed on the first GaN layer in contact with the first GaN layer, and a second GaN layer formed on the first AlN intermediate layer in contact with the first AlN intermediate layer.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: July 16, 2019
    Assignee: Air Water Inc.
    Inventors: Mitsuhisa Narukawa, Akira Fukazawa, Hiroki Suzuki, Keisuke Kawamura
  • Patent number: 10355164
    Abstract: A method of forming an electrical device that includes epitaxially growing a first conductivity type semiconductor material of a type III-V semiconductor on a semiconductor substrate. The first conductivity type semiconductor material continuously extending along an entirety of the semiconductor substrate in a plurality of triangular shaped islands; and conformally forming a layer of type III-V semiconductor material having a second conductivity type on the plurality of triangular shaped islands to provide a textured surface of a photovoltaic device. A light emitting diode is formed on the textured surface of the photovoltaic device.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: July 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Ning Li, Devendra K. Sadana, Ghavam G. Shahidi
  • Patent number: 10355079
    Abstract: Hydrogen atoms and crystal defects are introduced into an n-semiconductor substrate by proton implantation. The crystal defects are generated in the n-semiconductor substrate by electron beam irradiation before or after the proton implantation. Then, a heat treatment for generating donors is performed. The amount of crystal defects is appropriately controlled during the heat treatment for generating donors to increase a donor generation rate. In addition, when the heat treatment for generating donors ends, the crystal defects formed by the electron beam irradiation and the proton implantation are recovered and controlled to an appropriate amount of crystal defects. Therefore, for example, it is possible to improve a breakdown voltage and reduce a leakage current.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: July 16, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takashi Yoshimura, Masayuki Miyazaki, Hiroshi Takishita, Hidenao Kuribayashi
  • Patent number: 10347624
    Abstract: An electrical device that in some embodiments includes a substrate including a lateral device region and a vertical device region. A lateral diffusion metal oxide semiconductor (LDMOS) device may be present in the lateral device region, wherein a drift region of the LDMOS device has a length that is parallel to an upper surface of the substrate in which the LDMOS device is formed. A vertical field effect transistor (VFET) device may be present in the vertical device region, wherein a vertical channel of the VFET has a length that is perpendicular to said upper surface of the substrate, the VFET including a gate structure that is positioned around the vertical channel.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Alain Loiseau
  • Patent number: 10347557
    Abstract: The wiring board includes an insulating substrate having a main surface, an external electrode on the main surface and an outer edge portion of the insulating substrate, and a dissipating metal layer on the main surface of the insulating substrate, the dissipating metal layer having a greater area than the external electrode if viewed in a plan, the dissipating metal layer being adjacent to the external electrode and having a slit. The slit has an opening at an outer periphery of the dissipating metal layer. The external electrode faces the opening.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: July 9, 2019
    Assignee: KYOCERA CORPORATION
    Inventor: Kouichi Kawasaki
  • Patent number: 10347790
    Abstract: Light-emitting devices having a multiple quantum well (MQW) pin diode structure are provided. The light-emitting devices include a multilayered p-type contact composed of a heavily p-type doped hole injection layer and a thin p-type group III-nitride layer. The materials of the hole injection layer and the p-type group III-nitride layer are separated by a layer of a material that allows current tunneling through the heterogeneous junction formed between the lattice mismatched materials.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: July 9, 2019
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Zhenqiang Ma, Dong Liu
  • Patent number: 10332935
    Abstract: A storage apparatus according to embodiments includes: a first interlayer insulating film extending in a first direction; a second interlayer insulating film extending in the first direction; a first conductive layer extending in the first direction and provided between the first interlayer insulating film and the second interlayer insulating film; a second conductive layer extending in a second direction intersecting the first direction; a resistance change layer including a first portion provided between the first interlayer insulating film and the second interlayer insulating film and including a second portion provided between the second conductive layer and the first interlayer insulating film, between the second conductive layer and the first conductive layer, and between the second conductive layer and the second interlayer insulating film; and a sidewall insulating film provided between the first portion and the first interlayer insulating film and between the first portion and the second interlayer i
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: June 25, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki Ishikawa, Mutsumi Okajima, Takayuki Tsukamoto
  • Patent number: 10327499
    Abstract: A shoe is provided for use by a user and for use with a communication device that transmits a blood pressure signal based on a detected blood pressure of the user. The shoe includes a sole, a force actuating mechanism, a receiver and a controller. The sole has a top surface for supporting the foot of the user when being worn by the user. The force actuating mechanism provides a force normal to the top surface of the sole and is disposed at the sole so as to provide the force to a plantar venous plexus of the foot. The receiver receives the blood pressure signal. The controller generates a control signal to control the force actuating mechanism. The controller further modifies the control signal based on the received blood pressure signal.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: June 25, 2019
    Assignee: Under Armour, Inc.
    Inventors: Mark A. Oleson, F. Grant Kovach, Nathan Dau, Jeffrey Allen
  • Patent number: 10326089
    Abstract: The disclosure relates to a logic circuit. The logic circuit includes a n-type thin film transistor and a p-type thin film transistor. Each thin film transistor includes a substrate; a semiconductor layer including nano-scaled semiconductor materials; a source and a drain, wherein the source and the drain are spaced apart from each other, and electrically connected to the semiconductor layer; a dielectric layer covering the semiconductor layer, wherein the dielectric layer includes a normal dielectric layer and an abnormal dielectric layer stacked on one another, and the abnormal dielectric layer is an oxide dielectric layer grown by magnetron sputtering; and a gate in direct contact with the abnormal dielectric layer. The n-type thin film transistor and the p-type thin film transistor share the same substrate and the same gate.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: June 18, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Dan Zhao, Yu-Jia Huo, Xiao-Yang Xiao, Ying-Cheng Wang, Tian-Fu Zhang, Yuan-Hao Jin, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 10325778
    Abstract: A chemical material is deposited on a surface of a substrate. A mandrel composition is deposited on a surface of the chemical material. A mandrel hard mask pattern is deposited on a surface of the mandrel composition. The mandrel composition is etched. The mandrel hard mask pattern is removed. A plurality of spacer materials are deposited sequentially onto a surface of the chemical material and a surface of the mandrel composition. A portion of each of the plurality of spacer materials are removed sequentially. A remainder of the mandrel composition is removed. The substrate is etched. The chemical material and at least one of the spacer materials of the plurality of spacer materials are removed.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, John H. Zhang, Carl Radens
  • Patent number: 10325777
    Abstract: A chemical material is deposited on a surface of a substrate. A mandrel composition is deposited on a surface of the chemical material. A mandrel hard mask pattern is deposited on a surface of the mandrel composition. The mandrel composition is etched. The mandrel hard mask pattern is removed. A plurality of spacer materials are deposited sequentially onto a surface of the chemical material and a surface of the mandrel composition. A portion of each of the plurality of spacer materials are removed sequentially. A remainder of the mandrel composition is removed. The substrate is etched. The chemical material and at least one of the spacer materials of the plurality of spacer materials are removed.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, John H. Zhang, Carl Radens
  • Patent number: 10325843
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first lamination layer on a first side of a package substrate and a first surface finish on one or more electrical contacts disposed on a second side of the package substrate; removing the first lamination layer from the first side of the package substrate; depositing a second lamination layer on the second side of the package substrate and a second surface finish on the one or more electrical contacts disposed on the first side of the package substrate; and removing the second lamination layer from the second side of the package substrate. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: June 18, 2019
    Assignee: INTEL CORPORATION
    Inventors: Qinglei Zhang, Stefanie M. Lotz