Patents Examined by Hsien Ming Lee
  • Patent number: 11915936
    Abstract: A device includes a substrate, a gate structure over the substrate, gate spacers on opposite sidewalls of the gate structure, source/drain structures over the substrate and on opposite sides of the gate structure, and a self-assemble monolayer (SAM) in contact with an inner sidewall of one of the gate spacer and in contact with a top surface of the gate structure.
    Type: Grant
    Filed: January 11, 2023
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Wei Su, Fu-Ting Yen, Ting-Ting Chen, Teng-Chun Tsai
  • Patent number: 11908853
    Abstract: An integrated circuit includes a cell layer including a first cell and a second cell, a first metal layer over the cell layer and having a first conductive feature, a second metal layer over the first metal layer and having a second conductive feature, and a first via between the first metal layer and the second metal layer and connecting the first conductive feature to the second conductive feature. The first conductive feature spans over a boundary between the first and second cells, and has a lengthwise direction along a first direction. The second conductive feature spans over the boundary between the first and second cells, and has a lengthwise direction along a second direction that is perpendicular to the first direction.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fong-Yuan Chang, Kuo-Nan Yang, Chung-Hsing Wang, Lee-Chung Lu, Sheng-Fong Chen, Po-Hsiang Huang, Hiranmay Biswas, Sheng-Hsiung Chen, Aftab Alam Khan
  • Patent number: 11910597
    Abstract: Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Haitao Liu, Durai Vishak Nirmal Ramaswamy, Yunfei Gao, Sanh D. Tang, Deepak Chandra Pandey
  • Patent number: 11903180
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes providing a semiconductor substrate having a trench. The method also includes forming a first buffer layer in the trench. The method further includes forming a doped-polysilicon layer on the first buffer layer in the trench. The method also includes performing a thermal treatment on the doped-polysilicon layer.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: February 13, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Cheng-Yan Ji, Wei-Tong Chen
  • Patent number: 11903186
    Abstract: A semiconductor device and method for manufacturing the same are provided. The method includes providing a substrate including a plurality of active areas separated from each other. In some embodiments, the method also includes forming first mask structures on the substrate. In some embodiments, the method further includes forming a first protective layer covering the first mask structures and the substrate. In some embodiments, the first protective layer defines an area exposing a portion of the first mask structures and the substrate, and the area defined by the first protective layer has a zigzag edge in a top view. In addition, the method includes performing a first etching process to remove a portion of the substrate exposed from the first mask structures and the first protective layer to form trenches.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: February 13, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Yu-Ting Lin, Huei-Ru Lin
  • Patent number: 11901311
    Abstract: A method of fabricating a memory device includes patterning a stacked structure to form a first staircase structure and a second staircase structure; patterning a conductive layer under the stacked structure to form a first slit trench along a first direction; forming a first dielectric layer overlaying the first staircase structure and the second staircase structure and filling into the first slit trench, wherein the first dielectric layer filled in the first slit trench forms a first slit; patterning the first dielectric layer, the stacked structure, and the conductive layer to form multiple second slit trenches, wherein the second slit trenches along a second direction perpendicular to the first direction; performing a replacement process to replace the sacrificial layers with multiple gate conductive layers; and filling a second dielectric layer in the second slit trenches to form multiple second slits.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: February 13, 2024
    Assignee: MACRONIX International Co., Ltd.
    Inventor: Chin-Cheng Yang
  • Patent number: 11895820
    Abstract: The present application provides a method of manufacturing a memory device having a word line (WL) with improved adhesion between a work function member and a conductive layer. The method includes steps of providing a semiconductor substrate defined with an active area and including an isolation structure surrounding the active area; forming a recess extending into the semiconductor substrate and across the active area; forming a first insulating layer conformal to the recess; disposing a first conductive material conformal to the first insulating layer; forming a conductive member surrounded by the first conductive material; disposing a second conductive material over the conductive member and removing a portion of the first conductive material above the second conductive material to form a conductive layer enclosing the conductive member; and forming a second insulating layer over the conductive layer and conformal to the first insulating layer.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: February 6, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Yueh Hsu, Wei-Tong Chen
  • Patent number: 11894301
    Abstract: A vertical memory device includes a cell stacked structure, a wiring connection structure, and a first insulating interlayer. The cell stacked structure may include insulation layers and gate patterns repeatedly and alternately stacked on a first region of a substrate. The wiring connection structure may contact side walls of the cell stacked structure. The wiring connection structure may include a first staircase structure having one side of a stepped shape, a second staircase structure having one side of a stepped shape and disposed below the first staircase structure, and a first dummy staircase structure between the first and second staircase structures. The first and second staircase structures may be spaced apart from each other in the first direction, and both sides in the first direction of the first dummy staircase structure may have stepped shapes. The first insulating interlayer may be on the substrate to cover the wiring connection structure.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: February 6, 2024
    Inventor: Seungjun Shin
  • Patent number: 11889678
    Abstract: A method of manufacturing a buried word line structure includes: providing a semiconductor substrate; injecting target ions into the semiconductor substrate to form an injected region in the semiconductor substrate; annealing the semiconductor substrate including the injected region to convert the injected region into an insulation region; forming a word line trench in the insulation region; and filling the word line trench with a word line metal to form a buried word line structure.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: January 30, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Jian Yang
  • Patent number: 11882702
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory opening fill structures including a respective vertical semiconductor channel and a respective vertical stack of memory elements extending through the alternating stack in a memory array region, via contact structures contacting the stepped surfaces of the electrically conductive layers at each step in a staircase region, and a vertical stack of access transistors located between the staircase region and the memory array region.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: January 23, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Shinsuke Yada
  • Patent number: 11877449
    Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A channel hole extending vertically above a substrate and having a plum blossom shape in a plan view is formed. A continuous blocking layer, a continuous charge trapping layer, and a continuous tunneling layer each following the plum blossom shape are formed from outside to inside in this order along sidewalls of the channel hole. A plurality of separate semiconductor channels each disposed over part of the continuous tunneling layer at a respective apex of the plum blossom shape are formed.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: January 16, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Wanbo Geng, Lei Xue, Xiaoxin Liu, Tingting Gao, Weihua Cheng
  • Patent number: 11871555
    Abstract: A semiconductor structure and method for forming the semiconductor structure are provided. The method includes: providing a semiconductor substrate, which has a plurality of independent active areas that are isolated from each other by shallow trench isolation areas; forming trenches by etching the active areas and the shallow trench isolation areas, the trenches include first trenches and second trenches, the first trenches are located in the active areas, the second trenches are located in the shallow trench isolation areas, and the first trenches have a width greater than a width of the second trenches; forming word lines in the trenches, the word lines include first word lines and second word lines, each first word line is located in the respective first trench, each second word line is located in the respective second trench, and the first word lines have a width greater than a width of the second word lines.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: January 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Qu Luo, WenHao Hsieh
  • Patent number: 11858806
    Abstract: In described examples, a first metal layer is configured along a periphery of a cavity to be formed between a first substrate and a second substrate. A second metal layer is adjacent the first metal layer. The second metal layer includes a cantilever. The cantilever is configured to deform by bonding the first substrate to the second substrate. The deformed cantilevered is configured to impede contaminants against contacting an element within the cavity.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: January 2, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: John Charles Ehmke, Ivan Kmecko
  • Patent number: 11864385
    Abstract: Disclosed is a three-dimensional semiconductor memory device comprising intergate dielectric layers and electrode layers alternately stacked on a substrate, a vertical semiconductor pattern that penetrate the intergate dielectric layers and the electrode layers and extends into the substrate, blocking dielectric patterns between the vertical semiconductor pattern and the electrode layers, a tunnel dielectric layer between the blocking dielectric patterns and the vertical semiconductor pattern and in contact with the blocking dielectric patterns and simultaneously with the intergate dielectric layers, and first charge storage patterns between the blocking dielectric patterns and the tunnel dielectric layer. One of the first charge storage patterns is in contact with top and bottom surfaces of one of the blocking dielectric patterns.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: January 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seunghwan Lee, Suhyeong Lee, Ju-Young Lim, Daehyun Jang, Sanghoon Jeong
  • Patent number: 11864372
    Abstract: A method for reducing bending of word lines in a memory cell includes a) providing a substrate including a plurality of word lines arranged adjacent to one another and above a plurality of transistors; b) depositing a layer of film on the plurality of word lines using a deposition process; c) after depositing the layer of film, measuring word line bending; d) comparing the word line bending to a predetermined range; e) based on the word line bending, adjusting at least one of nucleation delay and grain size of the deposition process; and f) repeating b) to e) one or more times using one or more substrates, respectively, until the word line bending is within the predetermined range.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: January 2, 2024
    Assignee: Lam Research Corporation
    Inventors: Gorun Butail, Shruti Thombare, Ishtak Karim, Patrick Van Cleemput
  • Patent number: 11856763
    Abstract: A method of forming a microelectronic device including a first stack structure comprising alternating levels of insulative structures and other insulative structures, forming strings of memory cells through the first stack structure, forming a second stack structure over the first stack structure, based at least partially on observed amount of pillar bending within the first stack structure, forming a first tailored reticle specific to the observed amount of pillar bending, utilizing the first tailored reticle to form openings extending through the second stack structure and over some of the strings of memory cells, wherein centers of the openings over the strings of memory cells are at least substantially aligned with the centers of uppermost surfaces of the strings of memory cells in a direction of the observed pillar bending, and forming upper pillars extending through the second stack structure and over some of the strings of memory cells.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: December 26, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Lifang Xu, Sidhartha Gupta, Kar Wui Thong, Harsh Narendrakumar Jain
  • Patent number: 11856754
    Abstract: The present disclosure provides a method of manufacturing a semiconductor structure, a semiconductor structure, and a memory. The semiconductor structure includes a base. The base includes columnar basal bodies and an isolation layer filled around the columnar basal bodies. Word line trenches are provided in the base and extend along a direction parallel to a surface of the base. First trench portions are formed at parts of the word line trenches intersecting with the columnar basal bodies, and a first word line conductive layer, a second word line conductive layer, and an insulating layer are sequentially arranged in the first trench portions from bottom to top. Second trench portions are formed at parts of the word line trenches intersecting with the isolation layer, and the second word line conductive layer and the insulating layer are sequentially arranged in the second trench portions from bottom to top.
    Type: Grant
    Filed: August 2, 2023
    Date of Patent: December 26, 2023
    Assignee: Changxin Memory Technologies, Inc.
    Inventor: Jingwen Lu
  • Patent number: 11856752
    Abstract: A semiconductor device includes an active region in a substrate, an isolation film defining the active region in the substrate, a gate trench extending across the active region and the isolation film and including a first trench in the active region and a second trench in the isolation film, a gate electrode including a main gate electrode and a pass gate electrode, the main gate electrode filling a lower part of the first trench, and the pass gate electrode filling a lower part of the second trench, a support structure on the pass gate electrode, the support structure filling an upper part of the second trench, a gate insulating film interposed between the isolation film and the pass gate electrode and between the support structure and the pass gate electrode.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: December 26, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Ki-Hyung Nam
  • Patent number: 11842993
    Abstract: A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: December 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ying-Cheng Tseng, Yu-Chih Huang, Chih-Hsuan Tai, Ting-Ting Kuo, Chi-Hui Lai, Ban-Li Wu, Chiahung Liu, Hao-Yi Tsai
  • Patent number: 11844231
    Abstract: A display device includes a substrate, a plurality of pixels above the substrate, each of the pixels including a light emitting element, a display region including the plurality of pixels, a thin film transistor which each of the plurality of pixels includes, a protective film including a first inorganic insulating material and located between the thin film transistor and the light emitting element, a sealing film including a second inorganic insulating material and covering the light emitting element, and at least one through hole located in the display region and passing through the substrate, the protective film, and the sealing film, wherein the second inorganic insulating material is in direct contact with the protective film in a first region located between the through hole and the pixels.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: December 12, 2023
    Assignee: Japan Display Inc.
    Inventor: Heisuke Kanaya