Abstract: A semiconductor structure includes a first transistor comprising a first gate structure over a first active region in a substrate. The semiconductor structure further includes a second active region in the substrate. The semiconductor structure further includes a first butted contact. The butted contact includes a first portion extending in a first direction and overlapping the second active region, and a second portion extending from the first portion in a second direction, different from the first direction, wherein the second portion directly contacts the first gate structure.

Abstract: A luminescent material represented by Formula 1, a method of preparing the same, and a light-emitting device including the same: [A1nA23][B2][X1mX25]??Formula 1 A1, A2, B, X1, X2, n, and m in Formula 1 are as defined in the specification.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A sacrificial gate structure having sidewall spacers is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is removed. The second semiconductor layers are laterally recessed. Dielectric inner spacers are formed on lateral ends of the recessed second semiconductor layers. The first semiconductor layers are laterally recessed. A source/drain epitaxial layer is formed to contact lateral ends of the recessed first semiconductor layer. The second semiconductor layers are removed thereby releasing the first semiconductor layers in a channel region. A gate structure is formed around the first semiconductor layers.

Abstract: The application relates to a semiconductor switch element, including: a first vertical transistor device formed in a substrate and having a source region formed on a first side of the substrate and a drain region formed on a second side of the substrate vertically opposite to the first side; a second vertical transistor device formed laterally aside the first vertical transistor device in the same substrate and having a source region formed on the first side of the substrate and a drain region formed on the second side of the substrate; a conductive element arranged on the second side of the substrate and electrically connecting the drain regions of the vertical transistor devices; and a trench extending vertically into the substrate at the second side of the substrate, wherein at least a part of the conductive element is arranged in the trench.

Abstract: A semiconductor memory includes metallic lines on a substrate and including an uppermost metallic line, a semiconductor conduction line on the uppermost metallic line, a vertical structure penetrating the semiconductor conduction line and metallic lines, and including a vertical structure that includes an upper channel film, a first lower channel film, and an upper connection channel film connecting the upper channel film and the first lower channel film between a bottom of the semiconductor conduction line and a bottom of the uppermost metallic line, and a first cutting line through the metallic lines and the semiconductor conduction line, and including a first upper cutting line through the semiconductor conduction line, and a first lower cutting line through the plurality of metallic lines, a width of the first upper cutting line being greater than a width of an extension line of a sidewall of the first lower cutting line.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; an isolation structure, formed in the substrate; a word line (WL), a part of the WL being located in the isolation structure; and a conductive portion, located at a bottom of the isolation structure.

Abstract: A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.

Abstract: A 3D memory array includes a row of stacks, each stack having alternating gate strips and dielectric strips. Dielectric plugs are disposed between the stacks and define cell areas. A data storage film and a channel film are disposed adjacent the stacks on the sides of the cell areas. The middles of the cell areas are filled with an intracell dielectric. Source lines and drain lines form vias through the intracell dielectric. The source lines and the drain lines are each provided with a bulge toward the interior of the cell area. The bulges increase the areas of the source line and the drain line without reducing the channel lengths. In some of these teachings, the areas of the source lines and the drain lines are increased by restricting the data storage film or the channel layer to the sides of the cell areas adjacent the stacks.

Abstract: A three-way switch array structure including N first connectors, M second connectors, N×M third connectors and N×M three-way switches is provided, each three-way switch has a first terminal, a second terminal, a third terminal, a first switch and a second switch. Each of first terminals is disposed on one of the first connectors, each of second terminals is disposed on one of the second connectors, and each of third terminals is disposed on one of the third connectors, the first switch is disposed between the first terminal and the third terminal, and the second switch is disposed between the second terminal and the third terminal, wherein N and M are positive integers greater than or equal to 1.

Abstract: A three-dimensional memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate; a first stairway structure and a second stairway structure defined in the electrode structure, and positioned at different heights from each other; a sidewall of the electrode structure formed due to a difference in height between the first stairway structure and the second stairway structure; and a dielectric support passing through the electrode structure, and isolating a corner portion of the sidewall from the plurality of electrode layers.

Abstract: A semiconductor device includes a first stacked structure and a second stacked structure spaced apart from each other on a substrate, and a plurality of separation structures and a plurality of vertical memory structures alternately arranged between the first stacked structure and the second stacked structure in a first direction parallel to an upper surface of the substrate. Each of the first and second stacked structures includes a plurality of interlayer insulating layers and a plurality of gate layers alternately repeatedly stacked on the lower structure. Each of the vertical memory structures includes a first data storage structure facing the first stacked structure and a second data storage structure facing the second stacked structure. Side surfaces of the first and second stacked structures facing the vertical memory structures are concave in a plan view.

Abstract: A novel dielectric cap structure for VTFET device fabrication is provided. In one aspect, a method of forming a VTFET device includes: patterning fins in a substrate using fin hardmasks, including a first fin(s) and a second fin(s); depositing a liner over the fins and the fin hardmasks; selectively forming first hardmask caps on top of the fin hardmasks/liner over the first fin(s); forming first bottom source and drain at a base of the first fin(s) while the fin hardmasks/liner over the first fin(s) are preserved by the first hardmask caps; selectively forming second hardmask caps on top of the fin hardmasks/liner over the second fin(s); and forming second bottom source and drains at a base of the second fin(s) while the fin hardmasks/liner over the second fin(s) are preserved by the second hardmask caps. A device structure is also provided.

Abstract: There are provided a semiconductor memory device and an erasing method of the semiconductor memory device. The semiconductor memory device includes: a plurality of word lines stacked between a source conductive pattern and a bit line; at least two drain select lines disposed between the plurality word lines and the bit line, the at least two drain select lines being spaced apart from each other in an extending direction of the bit line; and an erase control line disposed between the at least two drain select lines and the plurality of word lines.

Abstract: A semiconductor storage device includes: a substrate having a front surface; a plurality of conductive layers arranged in a first direction, the first direction intersecting the front surface of the substrate; a plurality of memory cells connected to the plurality of conductive layers; a contact electrode extending in the first direction and connected to one of the plurality of conductive layers; and an insulating structure extending in the first direction, the insulating structure connected to an end portion of the contact electrode on one side of the contact electrode in the first direction, and penetrating the plurality of conductive layers.

Abstract: A substrate with a conductive film for manufacturing a reflective mask which has a rear-surface conductive film with high mechanical strength and is capable of correcting positional deviation of the reflective mask from the rear surface side by a laser beam or the like. A substrate with a conductive film has a conductive film formed on one surface of a main surface of a mask blank substrate used for lithography, wherein the conductive film includes a transparent conductive layer provided on a substrate side and an upper layer provided on the transparent conductive layer, the conductive film has a transmittance of 10% or more for light of wavelength 532 nm, the upper layer is made of a material including tantalum (Ta) and boron (B), and the upper layer has a film thickness of 0.5 nm or more and less than 10 nm.

Abstract: A semiconductor device includes: a first gate stack including a plurality of first gate electrodes; a second gate stack arranged on the first gate stack and including a plurality of second gate electrodes; and a plurality of channel structures arranged in a plurality of channel holes penetrating the first gate stack and the second gate stack. Each of the channel holes includes a first channel hole portion penetrating the first gate stack and a second channel hole portion penetrating the second gate stack, and a ratio of a second width in the second direction to a first width in the first direction of an upper end of the first channel hole portion is less than a ratio of a fourth width in the second direction to a third width in the first direction of an upper end of the second channel hole portion.

Abstract: Techniques herein include methods for fabricating complete field effect transistors having an upright or vertical orientation. The methods can utilize epitaxial growth to provide fine control over material deposition and thickness of said material layers. The methods can provide separate control of channel doping in either NMOS and/or PMOS transistors. All of a source, channel, and drain can be epitaxially grown in an opening into a dielectric layer stack, with said doping executed during said epitaxial growth.

Abstract: A method includes forming a gate structure and an interlayer dielectric (ILD) layer over a substrate; selectively forming an inhibitor over the gate structure; performing an atomic layer deposition (ALD) process to form a dielectric layer over the ILD layer, wherein in the ALD process the dielectric layer has greater growing rate on the ILD than on the inhibitor; and performing an atomic layer etching (ALE) process to etch the dielectric layer until a top surface of the inhibitor is exposed, in which a portion of the dielectric layer remains on the ILD layer after the ALE process is complete.

Abstract: A semiconductor device, and a method of manufacturing the semiconductor device, the method includes forming a first stack structure penetrated by first channel structures, forming electrode patterns surrounding second channel structures and separated from each other by first slits and second slits, the second channel structures coupled to the first channel structures, and the second slits comprising a different width from the first slits, filling each of the first slits and the second slits with an insulating material to cover sidewalk of the electrode patterns, and forming third slits passing through the insulating material in each of the second slits and extending to pass through the first stack structure.

Abstract: A method includes forming a cell layer including first and second cells, each of which is configured to perform a circuit function; forming a first metal layer above the cell layer and including a first conductive feature and a second conductive feature extending along a first direction, in which the first conductive feature extends from the first cell into the second cell, and in which a shortest distance between a center line of the first conductive feature and a center line of the second conductive feature along a second direction is less than a width of the first conductive feature, and the second direction is perpendicular to the first direction; forming a first conductive via interconnecting the cell layer and the conductive feature.