Abstract: A method of forming a two dimensional (2D) vertical fin is provided. The method includes heat treating a periodic array of irregular openings in a substrate, wherein there are walls of substrate material between adjacent openings, to reduce the surface area of the openings, and etching the openings with a crystal-plane selective etch to form squared openings in the substrate.

Abstract: Method for controlling the state of an operation in a hydrocarbon exploration and recovery environment, including creating at least one function model, said function model including at least one function, executing at least one function within said function model, defining a plurality of function controls, a pre-determined combination of given function controls within said plurality of function controls defining a signature event, an occurrence of said signature event being indicative of a specific state of said operation, and monitoring the occurrence of said signature event during execution of a certain function included in said at least one function model.

Abstract: A manufacturing method of a semiconductor structure is provided, and the manufacturing method includes the following operations. A first trench is formed on the semiconductor substrate, in which the first trench penetrates at least two of the conductive channels of a transistor, at least part of each of the conductive channels is located at the bottom of the first trench, an oxide layer is provided between two adjacent ones of the conductive channels, and each of the conductive channels has a bump structure in the first trench relative to the oxide layer. The shape of the bump structure of each of the conductive channels at the bottom of the first trench is adjusted by etching at the bottom of the first trench, so that the bump structure has at least two protrusions. A gate structure is formed in the first trench.

Abstract: In an embodiment, a device includes: a first insulating fin; a second insulating fin; a nanostructure between the first insulating fin and the second insulating fin; and a gate structure wrapping around the nanostructure, a top surface of the gate structure disposed above a top surface of the first insulating fin, the top surface of the gate structure disposed below a top surface of the second insulating fin.

Abstract: A substrate cleaning method includes: providing a substrate including a low-k layer containing silicon to a substrate support; etching the low-k layer by a plasma generated from a first gas; separating the etched substrate from the substrate support; and removing a reaction product attached to the substrate in the etching by a plasma generated from a second gas. The second gas includes a first carbon-containing gas represented by CxHyFz (y?0, x/z>¼).

Abstract: An integrated circuit device includes a substrate including an active region defined by a device isolation layer, the substrate defining a gate trench extending across the active region, a gate dielectric layer conformally covering an inner surface of the gate trench, and a gate electrode filling the gate trench on the gate dielectric layer. The gate electrode is composed of crystal grains of a single metal, and a diagonal length of at least one of the crystal grains is greater than a height of the active region that is in contact with the gate electrode.

Abstract: A film formation method includes (A) to (C) below. (A) Providing a substrate including, on a surface of the substrate, a first region in which a first material is exposed and a second region in which a second material different from the first material is exposed. (B) Supplying, to the surface of the substrate, vapor of a solution that contains a raw material of a self-assembled monolayer and a solvent by which the raw material is dissolved, and selectively forming a self-assembled monolayer in the first region. (C) Forming a desired target film in the second region by using the self-assembled monolayer formed in the first region.

Abstract: A method includes forming a dummy gate oxide on a wafer, and the dummy gate oxide is formed on a sidewall and a top surface of a protruding semiconductor fin in the wafer. The formation of the dummy gate oxide may include a Plasma Enhanced Chemical Vapor Deposition (PECVD) process in a deposition chamber, and the PECVD process includes applying a Radio Frequency (RF) power to a conductive plate below the wafer. The method further includes forming a dummy gate electrode over the dummy gate oxide, removing the dummy gate electrode and the dummy gate oxide to form a trench between opposing gate spacers, and forming a replacement gate in the trench.

Abstract: A method of fabricating semiconductor devices includes: loading one or more semiconductor wafers into a plurality of stations provided within a process chamber; applying a process to the semiconductor wafers which deposits a material on the one or more semiconductor wafers within the process chamber; and cleaning the process chamber. Suitably, cleaning the process chamber includes flowing a cleaning gas into the process chamber toward a deflector arranged in the process chamber, the deflector having a first surface upon which the flowed cleaning gas impinges, the first surface directing a first portion of the flowed cleaning gas impinging thereon in a first trajectory toward a first end of the process chamber and directing a second portion of the flowed cleaning gas impinging thereon in a second trajectory toward a second end of the process chamber, the second end being opposite the first end.

Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor substrate including a first and second regions; forming a first dielectric layer on the semiconductor substrate; forming a temporary layer on the first dielectric layer; performing a first heat treatment process on the first dielectric layer and the temporary layer; removing the temporary layer to expose the first dielectric layer; and performing a second heat treatment process on the first dielectric layer.

Abstract: The present disclosure provide a method that includes receiving a substrate having a semiconductor surface of a first semiconductor material; forming an APT feature in the substrate; performing a prebaking process to the substrate with a first temperature T1; epitaxially growing an undoped semiconductor layer of the first semiconductor layer and a first thickness t1 on the substrate at a second temperature T2; epitaxially growing a semiconductor layer stack over the undoped semiconductor layer at a third temperature T3 less than T2, wherein the semiconductor layer stack includes first semiconductor layers and second semiconductor layers stacked vertically in an alternating configuration; patterning the semiconductor substrate, and the semiconductor layer stack to form a trench, thereby defining an active region being adjacent the trench; forming an isolation feature in the trench; selectively removing the second semiconductor layers; and forming a gate structure wrapping around each of the first semiconductor

Abstract: Systems and methods for controlling device performance variability during manufacturing of a device on wafers are disclosed. The system includes a process platform, on-board metrology (OBM) tools, and a first server that stores a machine-learning based process control model. The first server combines virtual metrology (VM) data and OBM data to predict a spatial distribution of one or more dimensions of interest on a wafer. The system further comprises an in-line metrology tool, such as SEM, to measure the one or more dimensions of interest on a subset of wafers sampled from each lot. A second server having a machine-learning engine receives from the first server the predicted spatial distribution of the one or more dimensions of interest based on VM and OBM, and also receives SEM metrology data, and updates the process control model periodically (e.g., wafer-to-wafer, lot-to-lot, chamber-to-chamber etc.) using machine learning techniques.

Abstract: A photovoltaic structure includes: a hole-selective contact comprising an anodized aluminum layer overlaying a different electrode metal and a plurality of contact vias that extend through the anodized aluminum layer to the different electrode metal, wherein locations of the plurality of contact vias define an ordered array; an absorber comprising a chalcopyrite (Ag,Cu)(Ga, In)S,Se:Alk, where Alk represents at least one alkali element, the absorber comprising at least a residual of a contiguous nucleation template over the anodized aluminum layer; an electron-selective contact; and a plurality of nanorods located in the plurality of contact vias, the plurality of nanorods providing ohmic contacts between the hole-selective contact and the different electrode metal at their interface at a bottom of each contact via, and comprising at least a residual of at least one surfactant and at least a residual of at least one minority alloy constituent.

Abstract: Methods, systems, and devices for thin film transistor random access memory are described. A memory device may include memory cells each having one or more transistors formed above a substrate. For example, a memory cell may include a transistor having a channel portion formed by one or more pillars or other structures formed above a substrate, and a gate portion including a conductor formed above the substrate and configured to activate the channel portion based at least in part on a voltage of the gate portion. A memory cell may include a set of two or more such transistors to support latching circuitry of the memory cell, or other circuitry configured to store a logic state, which may or may not be used in combination with one or more transistors formed at least in part from one or more portions of a substrate.

Abstract: Threshold voltage (Vt) tuning layers may be sensitive to etching by reactants used to deposit overlying gate material, such as metal nitride. Methods for depositing Vt tuning layers are provided. In some embodiments Vt tuning layers may comprise a Vt tuning material in a neutral matrix. In some embodiments, processes for reducing or eliminating the etching of Vt tuning layers by halide reactants are described. In some embodiments a Vt tuning layer, such as a metal oxide layer, is treated by a nitridation process following deposition and prior to subsequent deposition of a metal nitride capping layer. In some embodiments an etch-protective layer, such as a NbO layer, is deposited over a Vt tuning layer prior to deposition of an overlying metal nitride layer.

Abstract: A vapor deposition mask made of metal includes: a front surface configured to oppose a vapor deposition source; and mask holes each including a hole portion having a shape of an inverted frustum. The hole portion of each of the mask holes includes: a small opening including a polygonal edge as seen from a view opposing the front surface of the vapor deposition mask, the edge including corners and linear portions each located between adjacent ones of the corners; and a large opening located on the front surface, the large opening including an edge as seen from the view opposing the front surface of the vapor deposition mask, the edge being shaped such that the corners of the edge of the small opening project outward from the edge of the small opening. The large opening surrounds the small opening as seen from the view opposing the front surface.

Abstract: A method of fabricating a semiconductor device includes providing a wafer inside a process chamber, performing an ALD (atomic layer deposition) process inside the process chamber to deposit titanium nitride on the wafer, providing a process gas used for the ALD process to a scrubber, filtering a first powder contained in the process gas, using a filter unit disposed in the scrubber and including a plurality of filters, adsorbing a second powder remaining in the process gas after passing through the filter unit, using a fin structure extending in a vertical direction inside the filter unit, and exhausting the process gas, from which the first and second powders are removed, from the scrubber.

Abstract: A technique for improving uniformity of film thickness on substrates, includes a substrate processing apparatus having a substrate retainer including substrate and partition plate supports; a reaction tube; a first driver vertically moving the substrate retainer into or out of the reaction tube; a second driver vertically moved by the first driver and rotating the substrate retainer to change a distance between a substrate and a partition plate by moving at least one of the substrate or the partition plate support; a heater; a gas supplier comprising a nozzle; a gas exhauster; and a controller controlling the first driver, the second driver and the gas supplier such that a gas is supplied to the substrate while changing at least one of a relative position of the substrate and a relative position of the partition plate with respect to a hole of the nozzle by driving the second driver.

Abstract: The present invention disclosures a critical dimension error analysis method, comprising: S01: performing lithography processes on a wafer, measuring the critical dimension (CD) values of the test points in each of the fields respectively; M and N are integers greater than 1; S02: removing extreme outliers from the critical dimension (CD) values; S03: rebuilding remaining CD values by a reconstruction model fitting method, and obtaining rebuilt critical dimension (CD?) values, according to relative error between CD? and CD, dividing the rebuilt critical dimension (CD?) values into scenes and the number of the scenes is A; S04: calculating components and corresponding residuals of the test points in each of the scenes under a reference system corresponding to a correction model by parameter estimation; S05: modifying machine parameters and masks by the correction model according to above calculation results.

Abstract: The present disclosure provide a semiconductor device and a method for preparing the semiconductor device. The semiconductor device includes a first buried gate structure and a second buried gate structure disposed in a semiconductor substrate. The first buried gate structure includes a first gate dielectric layer, and a first lower semiconductor layer disposed over the first gate dielectric layer. The first lower semiconductor layer has a T-shaped profile in a cross-sectional view. The first buried gate structure also includes a first upper semiconductor layer disposed over the first lower semiconductor layer. The second buried gate structure includes a second gate dielectric layer, and a second lower semiconductor layer disposed over the second gate dielectric layer. The second lower semiconductor layer has a U-shaped profile in the cross-sectional view. The second buried gate structure also includes a second upper semiconductor layer disposed over the second lower semiconductor layer.