Abstract: Provided herein is a semiconductor memory device exhibiting improved operating speed and a method of operating the semiconductor memory device. The semiconductor memory device may include a memory cell array, a peripheral circuit, and a control logic. The memory cell array may include a plurality of memory blocks. The peripheral circuit may perform a read operation on the memory cell array. The control logic may control an operation of the peripheral circuit. The control logic may control the peripheral circuit to perform a repair column masking operation on a selected memory block of the plurality of memory blocks, perform a first test operation on first drain select transistors included in the selected memory block, perform the first test operation on second drain select transistors different from the first drain select transistors while a result of the repair column masking operation remains.

Abstract: A method is provided of regulating a supply voltage for providing a bit line voltage in a semiconductor memory device where the bit line voltage is provided to memory cells in a bit line from the supply voltage through a bit switch. A bit line current provided to the memory cells is detected. The supply voltage is adjusted responsive to the deducted bit line current to at least partially compensate for a voltage drop across the bit switch where the voltage drop is dependent at least in part on the bit line current.

Abstract: For a memory cell, where an access transistor couples the memory cell to a local bit line, a pMOSFET essentially eliminates sub-threshold leakage current in the access transistor when the memory cell is not being read, and when the memory cell is being read, an additional pMOSFET essentially eliminates sub-threshold leakage current in the access transistor if the memory cell stores an information bit such that it does not discharge the local bit line. In this way, a half-keeper connected to the local bit line does not need to contend with sub-threshold leakage current.

Abstract: A high-density programmable logic device is presented, comprising two or more logic built-in blocks interconnected by a programmable global interconnect multiplex matrix. Each logic built-in block contains four groups of four macrocells and four I/O cells, two sub AND arrays and four sub OR arrays. Each sub OR array couples a group of macrocells, and each sub AND array drives two sub OR arrays. The sub AND and OR arrays can either function independently or be connected together by AND array or OR array connection facilities, to extend the logic capability. Every macrocell can be flexibly controlled by three levels of control signal: global, logic built-in block wide or separate. The outputs from the macrocells and the inputs from I/O cells can be fed locally back through the local feedback path, and also fed globally to other logic built-in blocks, through the global interconnect multiplex matrix.

Abstract: A synthesized oscillation circuit that can relax a limitation of the maximum operational frequency. A mixer (MX), a bandpass filter (BPF), an amplitude limiting amplifier (LIM), a phase detector (PD), a low-pass filter (LPF), and a voltage-controlled oscillator (VCO) are serially connected between a signal input terminal (IN) and a signal output terminal (OUT). The signal output terminal (OUT) is connected the mixer (MX) and the phase detector (PD). The bandpass filter (BPF) has a filtering characteristic which blocks the sum frequency component of the frequency component of an input signal from the signal input terminal (IN) to the mixer (MX) and the frequency component of an output signal from the voltage-controlled oscillator (VCO) to the mixer (MX), but which passes the difference frequency component between them.