Abstract: The conductor for a given signal in an integrated circuit (IC) is shielded from electromagnetic coupling with one or more other, potentially noisy on-chip signals by shielding structure that essentially surrounds the signal conductor in a Faraday cage. In one embodiment, the signal conductor lies in the outermost metal layer in the IC. In that case, the shielding structure is a pair of adjacent shielding conductors lying on either side of the signal conductor within the outermost metal layer and a subtending shielding conductor lying in a metal layer below the signal conductor and the two adjacent conductors, where the subtending conductor is electrically connected to each of the adjacent conductors via interlevel interconnects, but there are no active components in the IC that draw current from the shielding conductors. When configured for signal processing, the three shielding conductors are connected either directly or indirectly to a quiet external reference.

Abstract: An integrated circuit including a substrate having a memory area and a non-memory area. An embedded memory is fabricated on the substrate within the memory area. First and second semiconductor cells are fabricated on the substrate within the non-memory area. An electromagnetic shield covers substantially memory area. A routing layer is fabricated over the memory and non-memory areas and over the electromagnetic shield. A signal wire is electrically coupled between the first and second semiconductor cells and has a conductive segment which is routed within the routing layer and extends over the memory area.

Abstract: In a silicon substrate, impurity diffusion layers, serving as source and drain regions, are formed to be separated from each other. A gate insulation film is formed on the silicon substrate between these source and drain regions. The gate insulation film is a silicon oxide film containing Cl having concentration of more than 1.times.10.sup.18 atoms/cm.sup.3 and less than 2.times.10.sup.20 atoms/cm.sup.3, and the gate insulation film is formed on the silicon substrate by low-pressure CVD. A gate electrode, formed of a polysilicon layer, is formed on the gate insulation film. An inter-level insulation film is formed on a resultant structure. A contact hole is formed on each of the source and drain regions of the inter-level insulation film. A drain electrode is formed on the inter-level insulation film, and connected to the drain region through the contact hole. A source electrode is formed on the inter-level insulation film, and connected to the source region through the contact hole.

Abstract: An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween.

Abstract: A multiple well formation is provided in a CMOS region of a semiconductor substrate to provide enhanced latchup protection for one or more CMOS transistors formed in the wells. The structure comprises an N well extending from the substrate surface down into the substrate, a buried P well formed in the substrate beneath the N well, a second P well extending from the substrate surface down into the substrate, and an isolation region formed in the substrate between the N well and the second P well. The buried P well may extend beneath both the N well and the second P well in the substrate. In a preferred embodiment of the invention, the N well and the second P well are each implanted in the substrate at an energy level sufficient to provide a dopant concentration peak in the substrate below the depth of the isolation region to provide punch through protection and to provide a channel stop beneath the isolation region by proving a P-N junction between the N well and P well beneath the isolation region.

Abstract: A semiconductor device is provided in its base region with an emitter region consisting of a p-type first impurity layer having a first impurity concentration peak at a first depth and a p-type second impurity layer having an impurity concentration peak at a second depth, and ohmic contact is provided in the p-type second impurity layer. Due to this structure, the operability of an SRAM memory cell defining an emitter region of a bipolar transistor by a source/drain region of a MOS transistor can be improved.

Abstract: A pair of directly coupled Field Effect transistors (FETs), a latch of directly coupled FETS, a Static Random Access Memory (SRAM) cell including a latch of directly coupled FETs and the process of forming the directly coupled FET structure, latch and SRAM cell. The vertical FETs, which may be both PFETs, NFETs or one of each, are epi-grown NPN or PNP stacks separated by a gate oxide, SiO.sub.2. Each device's gate is the source or drain of the other device of the pair. The preferred embodiment latch includes two such pairs of directly coupled vertical FETs connected together to form cross coupled invertors. A pass gate layer is bonded to one surface of a layer of preferred embodiment latches to form an array of preferred embodiment SRAM cells. The SRAM cell may include one or two pass gates. The preferred embodiment SRAM process has three major steps. First, preferred embodiment latches are formed in an oxide layer on a silicon wafer.

Abstract: In an RF/microwave power amplifier comprising a linear array of MOSFET transistors in a semiconductor substrate, the transistors having gate and drain bond pads between adjacent transistors, drain to gate feedback capacitance is reduced by offsetting the drain bond pads from the gate bond pads. Bond wires to the drain bond pads extend in the offset direction from the drain bond pads, and bond wires to the gate bond pads extend from the gate bond pads in the opposite direction to reduce capacitive coupling between the bond wires and reduce the length of the bond wires.

Abstract: A subfield conductive layer is provided, wherein a conductive layer is implanted beneath and laterally adjacent a field dielectric. The subfield conductive layer is placed within the silicon substrate after the field dielectric is formed. The conductive layer represents a buried interconnect which resides between isolated devices. The buried interconnect, however, is formed using high energy ion implant through a field dielectric formed either by LOCOS or shallow trench isolation techniques. The buried interconnect, or conductive layer, resides and electrically connects source and drain regions of two isolated devices.

Abstract: A semiconductor device includes a gate electrode (4) formed of a conductive material on a semiconductor substrate (1) of one conductivity type with a gate insulating film (3) therebetween; first and second diffusion regions (5, 10) of another conductivity type formed on the semiconductor substrate (1) so as to sandwich the gate electrode (4); and a contact hole (17) for electrically connecting one (first) (10) of the first and second diffusion regions (5, 10) to a lower electrode (8) of a cell capacitor for storing charge therein, and has a characteristic that when a reverse voltage Vrev is applied as a junction application voltage between semiconductors of different conductivity types of the first diffusion region (10) and the semiconductor substrate (1) (positive potential is applied to the n-type semiconductor side and zero or negative potential, to the p-type semiconductor side), a leakage current Ileak flows between the first diffusion region (10) and the semiconductor substrate (1), and the junction app

Abstract: The present invention advantageously provides a method for forming a test structure for determining how LDD length of a transistor affects transistor characteristics. In one embodiment, a first polysilicon gate conductor is provided which is laterally spaced from a second polysilicon gate conductor. The gate conductors are each disposed upon a gate oxide lying above a silicon-based substrate. An LDD implant is forwarded into exposed regions of the substrate to form LDD areas within the substrate adjacent to the gate conductors. A first spacer material is then formed upon sidewall surfaces of both gate conductors to a first pre-defined thickness. Source/drain regions are formed exclusively within the substrate a spaced distance from the first gate conductor, the spaced distance being dictated by the first pre-defined thickness. A second spacer material is formed laterally adjacent to the first spacer material to a second pre-defined distance.

Abstract: A semiconductor processing method of forming a capacitor construction includes, a) providing a pair of electrically conductive lines having respective electrically insulated outermost surfaces; b) providing a pair of sidewall spacers laterally outward of each of the pair of conductive lines; c) etching material over the pair of conductive lines between the respective pairs of sidewall spacers selectively relative to the sidewall spacers to form respective recesses over the pair of conductive lines relative to the sidewall spacers, the etching leaving the outermost conductive line surfaces electrically insulated; d) providing a node to which electrical connection to a capacitor is to be made between the pair of conductive lines, one sidewall spacer of each pair of sidewall spacers being closer to the node than the other sidewall spacer of each pair; e) providing an electrically conductive first capacitor plate layer over the node, the one sidewall spacers, and within the respective recesses; and f) providing a

Abstract: A wafer structure and method of forming a wafer structure with all of the dielectric material and conducting material films removed from the outer periphery of the wafer in order to protect the dielectric and conducting films from damage due to wafer handling, storage, or clamping. The dielectric or conducting material is removed from the wafer edge using wafer edge exposure or edge bead rinse methods. The wafer edge exposure method is carried out at the same time the dielectric or conducting layer is being patterned.

Abstract: A semiconductor device (50) has a sensing element (30) and a transistor (40). The sensing element (30) is formed in a cavity (11) in a substrate (10). The sensing element (30) is formed in part using an epitaxial deposition process that fills the cavity (11) with a conductive material (18) such as polysilicon. A dielectric layer (17) is used to electrically isolate the sensing element (30) from the substrate (10).

Abstract: A process of forming a tungsten contact plug, on an integrated circuit (IC), that is substantially free of seam formation is described. The process includes forming a dielectric layer on a surface of a substrate, forming a via in the dielectric layer, blanket depositing a first bulk layer of tungsten on the dielectric layer and partially filling the via, blanket depositing an amorphous or a microcrystalline layer of tungsten over the first bulk layer of tungsten such that growth of tungsten grains inside the via is effectively inhibited, and blanket depositing a second bulk layer of tungsten on the amorphous or microcrystalline layer.

Abstract: A semiconductor device improves its electrical characteristics by reducing crystal defects in the vicinity of junction interfaces between a semiconductor layer, and a metal compound layer composed of semiconductor and metal elements, and between an epitaxial layer and its forming substrate. A pair of source/drain layers (52) are separately formed in a surface of a well layer (50), and a metal silicide layer (8) is formed thereon. A nitrogen inclusion region (9) is formed in the vicinity of a junction interface between the source/drain layers (52) and the metal silicide layer (8).

Abstract: The present invention is directed to a semiconductor device and method wherein a vertical opening is provided or formed completely through a semiconductor substrate of the semiconductor device to print an external electrical contact to be made to one of the semiconductor regions of the semiconductor substrate. In the disclosed embodiment an electrical contact is also provided to the bottom portion of the semiconductor substrate.

Abstract: A device structure comprising a resistor in a via opening between adjacent levels of metallization of a conventional field effect transistor (FET) by disposing amorphous (.alpha.) silicon between metal barrier layers, such as titanium tungsten and titanium nitride, at the via opening which is filled with a conductive material, such as tungsten, the device structure enabling a conventional FET and the resistor to only take the space of a conventional FET due to the unique properties of .alpha.-silicon.

Abstract: A semiconductor device in accordance with the present invention has a passivation film. The passivation film is provided on the entire surface of a substrate provided with a bonding pad and a scribe line. After applying a photoresist on the entire surface of the passivation film, a photoresist pattern is contoured. The photoresist pattern thus contoured is exposed and developed so as to be patterned. The photoresist is patterned so as to (1) provide an opening which is a connected region of a region to be the bonding pad and a region to be the scribe line, and (2) make angles of the patterning obtuse angles. Then, the passivation film is etched, and the photoresist is removed. With this arrangement, a removing solution and a resist residue do not remain in the opening section provided on a portion of the passivation film corresponding to the bonding pad, thereby preventing a quality deterioration such as corrosion of the bonding pad and breakage of wire bonding.