Patents Examined by Huy Phan
  • Patent number: 8710859
    Abstract: Disclosed is a method for testing multi-chip stacked packages. Initially, one or more substrate-less chip cubes are provided, each consisting of a plurality of chips such as chips stacked together having vertically connected with TSV's where there is a stacked gap between two adjacent chips. Next, the substrate-less chip cubes are adhered onto an adhesive tape where the adhesive tape is attached inside an opening of a tape carrier. Then, a filling encapsulant is formed on the adhesive tape to completely fill the chip stacked gaps. Next, the tape carrier is fixed on a wafer testing carrier in a manner to allow the substrate-less chip cubes to be loaded into a wafer tester without releasing from the adhesive tape. Accordingly, the probers of the wafer tester can be utilized to probe testing electrodes of the substrate-less chip cubes so that it is easy to integrate this testing method in TSV fabrication processes.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: April 29, 2014
    Assignee: Powertech Technology Inc.
    Inventor: Kai-Jun Chang
  • Patent number: 8363603
    Abstract: Apparatuses and methodologies are described that increase system capacity in a multi-access wireless communication system. Spatial dimensions may be utilized to distinguish between multiple signals utilizing the same channel and thereby increase system capacity. Signals may be separated by applying beamforming weights based upon the spatial signature of the user device-base station pair. Grouping spatially orthogonal or disparate user devices on the same channel facilitates separation of signals and maximization of user device throughput performance. User devices may be reassigned to groups periodically or based upon changes in the spatial relationships between the user devices and the base station.
    Type: Grant
    Filed: January 18, 2006
    Date of Patent: January 29, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Min Dong, Tingfang Ji, Dhananjay Ashok Gore, Alexei Gorokhov, Arak Sutivong
  • Patent number: 8189531
    Abstract: A wireless communication system is disclosed that includes plural wireless base stations that act as an origin wireless base station and a destination wireless base station, and a wireless mobile station. The origin wireless base station starts a handover process in response to movement of the wireless mobile station, attaches a header including transfer order information to transmission packet data addressed to the wireless mobile station, and transfers the transmission packet data with the header to the destination wireless base station. The destination wireless base station receives the transmission packet data with the header, determines whether a transfer order of the transmission packet data is correct based on the transfer order information included in the header, deletes the header from the transmission packet data upon determining that the transfer order is correct, and transmits the transmission packet data without the header to the wireless mobile station upon completion of the handover process.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: May 29, 2012
    Assignee: Fujitsu Limited
    Inventors: Teruyoshi Watanabe, Kazuo Kawabata
  • Patent number: 8159253
    Abstract: An exemplary method for manufacturing a liquid crystal display (LCD) includes providing an LCD panel (201) including a common voltage initialization circuit (2011); testing and inspecting the LCD panel for defects of the LCD panel, and thereby obtaining a preferred common voltage for the LCD panel; writing parameters of the preferred common voltage to the common voltage initialization circuit; and mounting a driving integrated circuit on the LCD panel, the driving integrated circuit being connected to the common voltage initialization circuit. The driving integrated circuit is connected to the common voltage initialization circuit.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: April 17, 2012
    Assignee: Chimei Innolux Corporation
    Inventor: Chien-Jen Chang
  • Patent number: 8093918
    Abstract: An electronic device that includes an actual operation circuit that operates during an actual operation of the electronic device, a second test circuit and a third test circuit that operate during a test of the electronic device, and a power supply section. The power supply section, during the actual operation of the electronic device, does not apply a power supply voltage to the second test circuit and applies power supply voltages to the actual operation circuit and the third test circuit. The power supply section, to obtain identification of the electronic device, applies a power supply voltage to the second test circuit.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: January 10, 2012
    Assignees: National University Corporation Tohoku University, Advantest Corporation
    Inventors: Toshiyuki Okayasu, Shigetoshi Sugawa, Akinobu Teramoto
  • Patent number: 8054087
    Abstract: Provided is a low-power direct current detector. The low-power direct current detector includes a main current source circuit generating an ultra-low current, a limitation circuit limiting the current generated by the main current source circuit to lower than a preset current, and a voltage detection circuit biased by the ultra-low current generated by the main current source circuit to detect an input DC voltage.
    Type: Grant
    Filed: November 19, 2008
    Date of Patent: November 8, 2011
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Joon Hyung Lim, Tah Joon Park
  • Patent number: 8046037
    Abstract: A mobile terminal including a first body, a second body slidably moveable with respect to the first body such that the first body is moved between a closed position and an open position, a connector electrically connecting the first body to the second body, and a slide module connecting the first body to the second body to allow the second body to move with respect to the first body between the closed position and the open position is provided. The slide module includes a first slide member connected to the first body, a second slide member connected to the second body, the second slide member being slidably connected to the first slide member, and a cover unit disposed between the first and second slide members, the cover unit being configured to prevent exposure of the connector when the first body is in the open position.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: October 25, 2011
    Assignee: LG Electronics Inc.
    Inventor: Chang-Yong Jang
  • Patent number: 8022709
    Abstract: A method and a system for determining a circular characteristic for distance protection of a three-phase electric line, the system comprising means for detecting a fault on the electric line, means for identifying a faulted phase or phases of the electric line, means for determining, at a measuring point, a first fault loop impedance by using voltage(s) of the faulted phase(s), a second fault loop impedance by using a polarization voltage and a third fault loop impedance by using predetermined line parameters, and means for determining a radius and midpoint of the circular characteristic.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: September 20, 2011
    Assignee: ABB Technology AG
    Inventors: Ari Wahlroos, Janne Altonen
  • Patent number: 8022718
    Abstract: A method of inspecting an electrostatic chuck (ESC) is provided. The ESC has a dielectric support surface for a semiconductor wafer. The dielectric support surface is scanned with a Kelvin probe to obtain a surface potential map. The surface potential map is compared with a reference Kelvin probe surface potential map to determine if the ESC passes inspection.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: September 20, 2011
    Assignee: Lam Research Corporation
    Inventors: Armen Avoyan, Hong Shih, John Daugherty
  • Patent number: 8018221
    Abstract: An apparatus for measuring an electric current flowing through an electrical conductor (1), comprising a measuring device which detects a magnetic field formed by the electrical conductor in three orthogonal spatial directions and supplies measurement signals associated with the respective spatial directions.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: September 13, 2011
    Assignee: Robert Seuffer GmbH & Co. KG
    Inventor: Rainer Dudzik
  • Patent number: 8018241
    Abstract: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: September 13, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 8013590
    Abstract: A method of measuring signals related to a photodiode based sensor and calculating a corrected data value thereof is disclosed. A nominal reset voltage value of the photodiode may be measured. A knee point voltage may be applied to the photodiode and resets a voltage on the photodiode to the knee point voltage when the voltage on the photodiode falls below the knee point voltage. Applying the knee point voltage may extend the dynamic range of the sensor. An output voltage of the photodiode at end of an integration time of the photodiode may be measured. The knee point voltage may be applied again after the end of the integration time. A voltage value of the photodiode of the knee point voltage may be measured. The nominal reset voltage value, the output voltage of a sensor and the knee point voltage may be reported to calculate the corrected data value.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: September 6, 2011
    Assignee: ON Semiconductor Trading, Ltd
    Inventor: Tom Walschap
  • Patent number: 8013621
    Abstract: Disclosed is an inspection method capable of performing an inspection of high reliability even for very fine and thin-film electrode pads of a target object, by using needle traces formed on the electrode pads and making the electrode pads repeatedly contact the probes at high accuracy. In the inspection method, under the control of a control unit 15 of an inspection apparatus 10, by using old needle traces formed on the respective pads P of the target object such as a semiconductor wafer W, contactable regions S for the probes 12A in preparation for a present inspection, so that each of the probes 12A contact each of the electrode pad P in the contactable region S and within an empty area with no needle trace.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: September 6, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Satoshi Sano, Daiki Kurihara
  • Patent number: 8013618
    Abstract: A voltage detection apparatus includes: a battery including unit cells mutually connected in series; a first block including at least one of the unit cells; a second block including at least one of the unit cells, and provided adjacent to the first block; a first voltage detector connected to the first block, which detects a voltage between both ends of the unit cell in the first block, and which includes: a current source; a current detection element connected to the current source; and a voltage measuring unit which detects a voltage between both ends of the current detection element; and a second voltage detector connected to the second block, which has a similar construction with the first voltage detector. An abnormality detector of the voltage detection apparatus detects an abnormality of the voltage detectors in accordance with the voltages between both ends of the current detection elements.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: September 6, 2011
    Assignee: Yazaki Corporation
    Inventors: Satoshi Ishikawa, Kimihiro Matsuura, Ryosuke Kawano
  • Patent number: 8013624
    Abstract: An electronic device test apparatus comprising: a test apparatus body for testing IC devices formed on a wafer for electrical characteristics; a probe card for electrically connecting the IC devices and the test apparatus body; a prober for pushing the wafer against the probe card so as to electrically connect the IC devices and the probe card; an abutting mechanism extending toward the back surface of the probe card and abutting against the back surface of the probe card; and a lock mechanism fixing the extension of the abutting mechanism in the state with the abutting mechanism abutting against the back surface of the probe card.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: September 6, 2011
    Assignee: Advantest Corporation
    Inventors: Katsuhiko Namiki, Shigeaki Naito
  • Patent number: 8013593
    Abstract: A voltage measuring apparatus for a semiconductor integrated circuit includes a first delay unit configured to delay a reference clock in a first region, a second delay unit configured to delay the reference clock in a second region and an analysis unit configured to analyze a difference in voltage level between the regions based on the phases of associated with the delayed clock signals generated by the first and second delay units.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: September 6, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hyung-Soo Kim, Yong-Ju Kim, Jong-Woon Kim, Hee-Woong Song, Ic-Su Oh, Tae-Jin Hwang
  • Patent number: 8008941
    Abstract: A polishing head is tested in a test station having a pedestal for supporting a test wafer and a controllable pedestal actuator to move a pedestal central wafer support surface and a test wafer toward the polishing head. In another aspect of the present description, the test wafer may be positioned using a positioner having a first plurality of test wafer engagement members positioned around the pedestal central wafer support surface. In another aspect, the wafer position may have a second plurality of test wafer engagement members positioned around an outer wafer support surface disposed around the pedestal central wafer support surface and adapted to support a test wafer. The second plurality of test wafer engagement members may be distributed about a second circumference of the ring member, the second circumference having a wider diameter than the first circumference. Additional embodiments and aspects are described and claimed.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: August 30, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Jeffrey P. Schmidt, Jay Rohde, Stacy Meyer
  • Patent number: 8008905
    Abstract: There is provided a waveform observing apparatus with a reduced depth in such a manner that the waveform observing apparatus is one including a terminal board, connecting wiring extending from external equipment, a memory for receiving measured data through the terminal board, to store the measured data, and a display for displaying the measured data in waveform, the apparatus including: a first intra-body substrate, installed in an erect state inside a body frame of the waveform observing apparatus; a plurality of first connectors, provided on the first intra-body substrate; and a measurement module, which is connector-connected to the first connector of the first intra-body substrate, to be installed between the first intra-body substrate and the terminal board, and also includes a measurement circuit, wherein a plurality of measurement modules are detachable in an aligned state with respect to the erect first intra-body substrate.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: August 30, 2011
    Assignee: Keyence Corporation
    Inventors: Takashi Atoro, Shinya Asada
  • Patent number: 8004297
    Abstract: The present disclosure includes various method, device, and system embodiments for isolation circuits. One such isolation circuit embodiment includes: a first transistor configured for connection to a supply voltage via a first terminal; a register connected to the first transistor; a second transistor in parallel with a resistor, wherein the second transistor is configured for connection to the first terminal, with a gate of the second transistor configured for connection to an output of the register; and wherein the second transistor is configured for connection to a second terminal, the second transistor having a state that depends on a status of the register.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: August 23, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Hani S. Attalla, Daniel P. Cram
  • Patent number: 8004282
    Abstract: A transient electromagnetic wave is generated using an electromagnetic instrument in a borehole. An apparent resistivity is estimated using a received signal responsive to the generated wave and further used to estimate a resistivity property of a fluid in the borehole.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: August 23, 2011
    Assignee: Baker Hughes Incorporated
    Inventor: Gregory B. Itskovich