Abstract: Protective caps are formed over horizontally closely spaced apart metal lines of an integrated circuit structure. Low k silicon oxide dielectric material is then deposited over and between the metal lines and over protective caps on the lines. After the formation of such low k material between the lines and over the caps, standard k dielectric material is deposited over the low k layer as a planarizing layer over low portions of the low k layer between the lines which may be lower than the top of the caps on the lines to prevent further etching or dishing of the low k layer of during planarizing. The structure is then planarized to bring the low k dielectric material down to the tops of the protective caps on the metal lines. A layer of standard k silicon material is then formed over the planarized low k layer and the caps to allow via formation without passing through the low k layer to avoid via poisoning.
Type:
Grant
Filed:
June 27, 2001
Date of Patent:
May 6, 2003
Assignee:
LSI Logic Corporation
Inventors:
John Rongxiang Hu, Kai Zhang, Senthil K. Arthanari, Hong-Qiang Michael Lu