Abstract: A method for manufacturing a semiconductor device enables the formation of a well optimized for a fine MOS transistor and a well formed deep with a relatively low concentration for a high voltage MOS transistor without increasing the number of manufacturing steps. The method for manufacturing a semiconductor device includes the steps of: forming a first ion implantation expendable film and an etching mask film on a first conductive type semiconductor substrate; patterning the etching mask film into a shape of an active and field region; introducing dopant into the substrate; forming a trench groove on the substrate; forming an insulation film in the trench groove; forming a first well; flattening the insulation film; removing the etching mask film; removing the expendable film; forming a second ion implantation expendable film on the substrate; forming a mask pattern; and forming a second well by introducing dopant into the substrate.

Abstract: A process forms a power semiconductor device with reduced input capacitance and improved switching speed. A substrate with an epitaxial has an oxide layer patterned to form a narrow terraced gate. A gate oxide layer is formed on the upper surface of the epitaxial layer. A layer of polysilicon is deposited on the narrow terraced gate oxide region and the gate oxide layer. The polysilicon layer is anisotropically etched to form polysilicon spacers abutting each of the two side surfaces of the narrow terraced gate region. A p-type dopant is implanted through the gate oxide layer and the polysilicon spacers and is driven in to form P-well regions in the epitaxial layer. A source mask is formed and an n-type dopant is implanted through the gate oxide layer and the polysilicon spacers. It is driven in to form N+ source regions in the P-well regions.

Abstract: A method for manufacturing a semiconductor device, includes forming a film on a substrate to be processed in a reaction furnace at a first temperature, unloading the substrate from the reaction furnace, and lowering a temperature in the reaction furnace to a second temperature which is lower than the first temperature, conducting a gas purge, using only an inert gas, in the reaction furnace after the substrate has been unloaded from the reaction furnace.

Abstract: Bipolar transistors of different designs, particularly designs optimized for different high frequency applications are formed on the same substrate by separate base layer formation processes for epitaxial growth including different material concentration profiles of germanium, boron and/or carbon. Epitaxial growth of individual growth layers by low temperature processes is facilitated by avoiding etching of the silicon substrate including respective collector regions through use of an etch stop that can be etched selectively to silicon. Annealing processes can be performed between growth of respective base layers and/or performed collectively after all transistors are substantially completed.

Abstract: Gap-fill and damascene methods are disclosed for depositing an insulating thin film of nitrofluorinated silicate glass on a substrate in a process chamber. A high-density plasma, generated from a gaseous mixture of silicon-, fluorine-, oxygen-, and nitrogen-containing gases, deposits a layer of nitrofluorinated silicate glass onto the substrate. For gap-fill applications, the substrate is biased with a bias power density between 4.8 and 11.2 W/cm2 and the ratio of flow rate for the oxygen-containing gas to the combined flow rate for all silicon-containing gases in the process chamber is between 1.0 and 1.8, preferably between 1.2 and 1.4. For damascene applications, the bias power density is less than 3.2 W/cm2, preferably 1.6 W/cm2, and the flow rate ratio is between 1.2 and 3.0. Using optimized parameters, the thin film has a lower dielectric constant and better adhesion properties than fluorosilicate glass.

Abstract: A semiconductor package which includes: a semiconductor integrated circuit having chip pads formed thereon; interconnection bumps overlying on the chip pads; a patterned metal layer connecting to the interconnection bumps; a first dielectric layer under the patterned metal layer; a second dielectric layer overlying on the patterned metal layer; and terminal pads connecting to the patterned metal layer. The semiconductor package can further include external terminals connecting to the terminal pads, a third dielectric layer filling a gap between the first dielectric layer and the semiconductor integrated circuit.

Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.

Abstract: The present invention provides a method of forming a shallow trench isolation structure in a substrate. The method comprises the steps of: forming an isolation silicon oxide film which comprises an upper portion extending over a silicon oxide film over a silicon nitride film and a lower portion extending in a trench in a silicon substrate; and carrying out an isotropic etching to said upper portion of said isolation silicon oxide film and said silicon oxide film, thereby forming an isolation trench structure without divots in said trench in said silicon substrate.

Abstract: A phosphor composition absorbs ultraviolet radiation and emits a green visible light. The phosphor composition comprises at least one of: Ba2SiO4:Eu2+; Ba2MgSi2O7:Eu2+; Ba2ZnSi2O7:Eu2+; BaAl2O4:Eu2+; SrAl2O4:Eu2+; and BaMg2Al16O27:Eu2+,Mn2+. Further, when the green-light emitting phosphor is combined with appropriate red and blue phosphors in a phosphor conversion material blend, and the phosphor conversion material blend absorbs ultraviolet radiation, and emits a bright white light with high brightness and quality. The ultraviolet radiation source may comprise a semiconductor ultraviolet radiation source.

Abstract: A power MOSFET suitable for use in RF applications and a method for making the same is disclosed. The power MOSFET reduces the gate coverage of the drain region of the device in order to decrease the device gate to drain capacitance Cgd. A significant portion of the gate overlaying the drain region is eliminated by the removal of a portion of a polysilicon layer that is disposed over a substantial portion of the drain region that resides between the channel portions of the body regions of the device. The resulting open area, that is subsequently covered by an oxide layer, separates the polysilicon gate electrodes of the device. Finally, a metal layer is deposited over the entire structure to form the gate and source electrodes of the device.

Abstract: The present invention provides three embodiments to deposit layers over a substrate using ultrasound energy to vibrate the substrate during (1) PVD or CVD deposition, (2) anneal or (3) plating deposition. The first embodiment deposits a first layer over a substrate using ultrasonic energy to vibrate the substrate. The ultrasound allows the layer to deposit more conformal over opening sidewalls and decreases overhangs and voids. The second embodiment involves using ultrasonic vibrations during annealing or RTA. The ultrasound smooches out barrier/seed/conductive layers in contact holes. The third embodiment is a method of plating a metal layer such as Cu over a substrate while vibrating the substrate with ultrasonic waves. The substrate is vibrated with ultrasound waves in vertical or horizontal direction. The ultrasonic vibration allow the metal to plate in small contact holes with improved step coverage.