Abstract: Methods, systems, and devices for commands to support adaptive memory systems are described. A memory system may be configured to receive a command to perform an operation on an address of a memory system, the command including an indication of a count of program/erase cycles associated with the address; determine whether the count of program/erase cycles associated with the address satisfies a threshold; adjust a trim parameter for operating the memory system based at least in part on determining that the indication of the count of program/erase cycles satisfies the threshold; and perform the operation associated with the command using the adjusted trim parameter.

Abstract: An electronic system includes an auxiliary processor. The auxiliary processor includes a remapping device which receives data through a direct memory access (DMA, a register unit which stores the data, and processing logic which transmits operating status information to the remapping device. The remapping device remaps position information in which the data is stored in the register unit on the basis of the operating status information.

Abstract: In at least some embodiments, a system comprises a processor and a direct memory access (DMA) subsystem coupled to the processor. The system further comprises a component coupled to the DMA subsystem via an interconnect employing security rules, wherein, if the component requests a DMA channel, the DMA subsystem restricts usage of the DMA channel based on the security rules.

Abstract: A transmitter includes a pull-down circuit coupled between an output of the transmitter and a first rail, a first pull-up circuit coupled between a second rail and the output of the transmitter, and a second pull-up circuit coupled between the second rail and the output of the transmitter. The transmitter also includes a control circuit coupled to a control input of the first pull-up circuit and a control input of the second pull-up circuit. The control circuit is configured to output a first control signal to the control input of the first pull-up circuit, wherein the first control signal controls a drive strength of the first pull-up circuit. The control circuit is also configured to output a second control signal to the control input of the second pull-up circuit, wherein the second control signal controls a drive strength of the second pull-up circuit.

Abstract: An AFSM core includes a destination state-cell generating a destination state-signal, and a source state-cell generating a source state-signal and causing transition of the source state-signal in response to an acknowledgement indicating transition of the destination state-signal. The acknowledgment is communicated through a delay. A state-overlap occurs between transition of the destination state-signal and transition of the source state-signal. An output-net includes a balanced logic-tree receiving inputs, including the destination state-signal, from the core, and an additional logic-tree cascaded with the balanced logic-tree to form an unbalanced logic-tree so an input to the additional logic-tree is provided by output from the balanced logic-tree and another input receives the source state-signal. Tree propagation time occurs between receipt of a transition in the destination state-signal by the balanced logic-tree and a resulting transition of the output from the balanced logic-tree.

Abstract: A bus architecture is disclosed that provides for transaction queue reallocation on the modules communicating using the bus. A module can implement a transaction request queue by virtue of digital electronic circuitry, e.g., hardware or software or a combination of both. Some bus clogging issues that affect conventional systems can be circumvented by combining an out of order system bus protocol that uses a transaction request replay mechanism. Modules can evict less urgent transactions from transaction request queues to make room to insert more urgent transactions. Master modules can dynamically update a quality of service (QoS) value for a transaction while the transaction is still pending.

Abstract: A device for a vehicle may include a first wireline interface configured to receive a first data stream from a first sensor having a first sensor type for perceiving a surrounding of the vehicle, the first data stream including raw sensor data detected by the first sensor; a second wireline interface configured to receive a second data stream from a second sensor having a second sensor type for perceiving the surrounding of the vehicle, the second data stream including raw sensor data detected by the second sensor; one or more processors configured to generate a coded packet including the received first data stream and the received second data stream by employing vector packet coding on the first data stream and the second data stream; and an output wireline interface configured to transmit the generated coded packet to one or more target units of the vehicle.

Abstract: Systems and methods for automated tuning of Quality of Service (QoS) settings of volumes in a distributed storage system are provided. According to one embodiment, one or more characteristics of a workload of a client to which a storage node of multiple storage nodes of the distributed storage system is exposed are monitored. After a determination has been made that a characteristic meets or exceeds a threshold, (i) information regarding multiple QoS settings assigned to a volume of the storage node utilized by the client is obtained, (ii) a new value of a burst IOPS setting of the multiple QoS settings is calculated by increasing a current value of the burst IOPS setting by a factor dependent upon a first and a second QoS setting of the multiple QoS settings, and (iii) the new value of the burst IOPS setting is assigned to the volume for the client.

Abstract: A data communication apparatus comprises a line driver configured to couple the data communication apparatus to a 1-wire serial bus; and a controller configured to: transmit a plurality of synchronization pulses over the 1-wire serial bus after a sequence start condition (SSC) has been transmitted over the 1-wire serial bus, the plurality of synchronization pulses being configured to synchronize one or more receiving devices coupled to the 1-wire serial bus to an untransmitted transmit clock signal; initiate an interrupt handling procedure when the plurality of synchronization pulses is encoded with a first value; and initiate a read transaction or a write transaction with at least one of the one or more receiving devices coupled to the 1-wire serial bus when the plurality of synchronization pulses is encoded with a second value.

Abstract: Systems, apparatuses, and methods related to memory systems and operation are described. A memory system may be coupled to a processor, which includes a memory controller. The memory controller may determine whether targeting of first data and second data by the processor to perform an operation results in processor-side cache misses. When targeting of the first data and the second data result in processor-side cache misses, the memory controller may determine a single memory access request that requests return of both the first data and the second data and instruct the processor to output the single memory access request to a memory system via one or more data buses coupled between the processor and the memory system to enable processing circuitry implemented in the processor to perform the operation based at least in part on the first data and the second data when returned from the memory system.

Abstract: Example implementations relate to executing a workload in a computing system including processing devices, memory devices, and a circuit switch. An example includes identifying first and second instruction-level portions to be consecutively executed by the computing system; determining a first subset of processing devices and a first subset of memory devices to be used to execute the first instruction-level portion; controlling the circuit switch to interconnect the first subset of processing devices and the first subset of memory devices during execution of the first instruction-level portion; determining a second subset of the processing devices and a second subset of the memory devices to be used to execute the second instruction-level portion; and controlling the circuit switch to interconnect the second subset of processing devices and the second subset of memory devices during execution of the second instruction-level portion.

Abstract: Embodiments of the present disclosure relate to application partitioning for locality in a stacked memory system. In an embodiment, one or more memory dies are stacked on the processor die. The processor die includes multiple processing tiles and each memory die includes multiple memory tiles. Vertically aligned memory tiles are directly coupled to and comprise the local memory block for a corresponding processing tile. An application program that operates on dense multi-dimensional arrays (matrices) may partition the dense arrays into sub-arrays associated with program tiles. Each program tile is executed by a processing tile using the processing tile's local memory block to process the associated sub-array. Data associated with each sub-array is stored in a local memory block and the processing tile corresponding to the local memory block executes the program tile to process the sub-array data.

Abstract: A storage engine has a pair of compute nodes, each compute node having a separate PCIe root complex and attached memory. The PCIe root complexes are interconnected by multiple Non-Transparent Bridge (NTB) links. The NTB resources are unequally shared, such that host IO devices are required to use a first subset of the NTB links to implement memory access operations on the memory of the peer compute node, whereas storage software memory access operations are able to be implemented on all of the NTB links. A NTB link arbitration system arbitrates usage of the first and second subsets of NTB links by the storage software, to distribute subsets of the storage software memory access operations on peer memory to the first and second subsets of NTB links, while causing all host IO device memory access operations on peer memory to be implemented on the first set of NTB links.

Abstract: Some aspects as disclosed herein are directed to, for example, a system and method of providing flexible surge volume management to applications when performance capacity is available. The system and method may comprise determining when a data surge is occurring and in response determining available performance capacity and automatically allocating, the available performance capacity, to storage group applications performing data operations.

Abstract: A technique is configured to provide various data protection schemes, such as replication and erasure coding, for data blocks of volumes served by storage nodes of a cluster configured to perform deduplication of the data blocks. Additionally, the technique is configured to ensure that each deduplicated data block complies with data redundancy guarantees of the data protection schemes, while improving storage space of the storage nodes. In order to satisfy the data integrity guarantees while improving available storage space, the storage nodes perform periodic garbage collection for data blocks to optimize storage in accordance with currently applicable data protection schemes.

Abstract: A memory device includes: a memory cell array including a first memory cell group including memory cells located within a first physical distance from a reference node and a second memory cell group including memory cells located beyond the first physical distance from the reference node; a peripheral circuit configured to perform a program operation of applying program voltages increasing gradually to memory cells included in the memory cell array through word lines; and control logic configured to determine a time at which a first program permission voltage is applied to the first memory cell group and determine a magnitude of the first program permission voltage on the basis of a magnitude of the program voltages in response to a gradual increase in the program voltages, the control logic is further configured to control the peripheral circuit to apply the first program permission voltage to the first memory cell group through bit lines.

Abstract: Systems, methods, and apparatus for memory device security and row hammer mitigation are described. A control mechanism may be implemented in a front-end and/or a back-end of a memory sub-system to refresh rows of the memory. A row activation command having a row address at control circuitry of a memory sub-system and incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system may be received. Control circuitry may determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count may be incremented each time the CAM is full. A refresh command to the row address may be issued when a determination is made that the first count is greater than the RHT minus the second count.

Abstract: Systems, apparatuses, and methods related to memory systems and operation are described. A memory system may be communicative coupled to a processor via one or more data buses. Additionally, the memory system may include one or more memory devices that store data to be used by processing circuitry implemented in the processor to perform an operation. Furthermore, the memory system may include a memory controller that receives a memory access request that return of the data via the one or more data buses and, in response, determines a storage location of the data in the one or more memory devices based at least in part on the memory access request and instructs the memory system to store the data directly into a processor-side cache integrated with the processing circuitry to enable the processing circuitry implemented in the processor to perform the operation based on the data.

Abstract: A storage device includes a memory device including a first memory region, a second memory region, and a third memory region, the first memory region having a lowest bit-density relative to the second memory region and the third memory region, a second memory region having a medium bit-density relative to the first memory region and the third memory region, and a third memory region having a highest bit-density relative to the first memory region and the second memory region; and a controller configured to control the memory device The controller is configured to distribute data received from a host to the first to third memory regions based on attributes of the data, to determine a current state based on a data distribution amount for each of the first to third memory regions and a respective size of each of the first to third memory regions, and to perform an action of increasing or decreasing a size of the second memory region under the current state based on a reinforcement learning result for mitigating

Abstract: Host access to a system DS1 can be configured for a logical device L1 so that L1 is exposed to the host over path P1 from DS1. Prior to configuring host access to L1 on another system DS2, configuration information of DS1 can be updated to include a fully populated uniform host configuration for the host with respect to L1. The fully populated uniform host configuration can identify P1 as well as path P2 between DS2 and the host. Even though P2 may not be established so that L1 is not yet exposed to the host over P2, DS1 can use the information included in the fully populated uniform host configuration to report information to the host regarding path state information for P1 and P2. The host can directly query DS2 regarding P2 in order to determine current up-to-date information regarding the path state of P2 with respect to L1.