Abstract: Testing of a computer-implemented dynamic content generator module operable within a computer networking environment is disclosed. According to an example, the dynamic content generator module executed by a computing system dynamically generates a content item for a test group based on a combination of test values of the test group as input to a template-rule framework. The dynamic content generator module outputs the content item for each test group. A testing module executed by the computing system associates the content item with the test values of the test group from which that content item was generated to obtain associated test result data, and outputs the associated test result data that includes the content item and associated test values.

Abstract: Systems, apparatuses, and methods can include a multi-stage cache for providing high reliability, availability, and serviceability (RAS). The multi-stage cache memory comprises a shadow DRAM, which is provided on a volatile main memory module, coupled to a memory controller cache, which is provided on a memory controller. During a first write operation, the memory controller writes data with a strong error correcting code (ECC) from the memory controller cache to the shadow DRAM without writing a RAID (Redundant Arrays of Inexpensive Disks) parity data. During a second write operation, the memory controller writes the data with the strong ECC and writes the RAID parity data from the shadow DRAM to a memory device provided on the volatile main memory module.

Abstract: Memory with address-selectable data poisoning circuitry is disclosed herein. In one embodiment, a memory device comprises circuitry operably connected to a memory array. The circuitry can include memory row address registers and/or memory column address registers. Standard access commands or mode register write commands can be used to load a memory row address or a memory column address into the memory row address registers or the memory column address registers, respectively. During a read operation directed to a second memory row and/or column of the memory array, the circuitry can compare the second memory row to the first memory row and/or the second memory column to the first memory column, and can poison a data bit read from the memory array before the data bit is output from the memory device when the first and second memory row addresses match and/or when the first and second memory column addresses match.

Abstract: A processing system includes a processing device coupled to a memory configured to check for and correct faults in requested data. In response to correcting the faults of the requested data, the memory sends the corrected data and unused check bits to the processing device as a plurality of fetch returns. The memory also sends a parity fetch based on the corrected data and one or more operations to the processing device. After receiving the plurality of fetch returns and the unused check bits, the processing device checks each fetch return for faults based on the unused check bits. In response to determining that a fetch return includes a fault, the processing device erases the fetch return and reconstructs the fetch return based on one or more other received fetch returns and the parity fetch.

Abstract: Provided herein are an error detection device and an error detection method to intuitively identify the reason for a handshake failure. An entire state transition flow including each state based on the communication standard and a state transition condition to be executed between states is displayed as a state transition setting screen, and an immediately preceding state in which the state transition fails and the failed state transition condition are highlighted on the state transition setting screen, when the handshake with the device under test ends.

Abstract: Methods, systems, and computer-readable media are disclosed herein combine randomization functionalities with the machine-learning prioritization of workflows for performance testing. In aspects, a primary workflow having a sequence of user interface steps is input. Testing workflows are generated that represent each variable position of unlocked steps in the sequence of the primary workflow while maintaining the sequential position of any locked steps. These testing workflows are then ingested to a machine learning model that identifies as subset of the testing workflows to prioritize over other. Specifically, testing workflows are prioritized that at least partially match sequence patterns in historical workflow data that is associated with vulnerable computer code. The subset is output and tested by testing engine to generate a report of any vulnerable computer code.

Abstract: A neural processing unit (NPU) is capable of testing a component of the NPU in a running system, i.e., during runtime. The NPU includes a plurality of functional components, each of which includes an electronic circuit; at least one wrapper connected to at least one of the functional components; and an in-system component tester (ICT). The ICT performs a selection of one of the at least one functional component, in an idle state, as a component under test (CUT) and performs a test, via the at least one wrapper, of the selected functional component. The ICT may monitor states of the plurality of the functional components via the at least one wrapper, stop the test based on a detection of a collision due to an access to the selected functional component, and return a connection of the selected functional component to the at least one wrapper according to the stop.

Abstract: An information handling system may include a host processor module comprising a host processor field programmable gate array, a management controller communicatively coupled to the host processor field programmable gate array and configured to provide out-of-band management facilities for management of the information handling system, and an interposer configured to interface between the host processor field programmable gate array and one or more peripheral devices in order to perform power management and control of the one or more peripheral device. The interposer may include a general purpose input/output extender configured to enable and control power delivery to the one or more peripheral devices and a microcontroller unit communicatively coupled to the host processor field programmable gate array and configured to perform monitoring and discovery of the one or more peripheral devices.

Abstract: A method includes decoding, by at least one hardware processor, a notification of a changed database code of a database. A query is executed responsive to the notification. The query indicates a data processing command and a data object in the database. A regression in the changed database code is detected based on multiple regression testing operations applied to the data processing command and the data object. Analysis of the regression is performed to detect a rollout parameter of a plurality of rollout parameters as a root cause of the regression. The plurality of rollout parameters are associated with the changed database code. A determination is made on whether to perform a mitigation action for the regression based on the rollout parameter.

Abstract: A method of error logging includes: receiving from a user interface a first input from a user indicating that they have seen a visible error in a displayed graphical output of a computer application, tracking the gaze of the user to estimate the position, on at least a first display showing at least part of the displayed graphical output, at which the user's gaze is directed, receiving from the user interface a second input from the user indicating that they have identified the visible error with their gaze, capturing data relating to the displayed graphical output of the computer application, the data including a capture of at least part of the displayed graphical output including the identified visible error, and the estimated positon of the user's gaze with respect to the displayed graphical output, and generating an error report including the captured data.

Abstract: An information handling system includes multiple dual in-line memory modules (DIMMs) and a basic input/output system (BIOS). The DIMMs form a memory system of the information handling system. The BIOS begins a system boot of the information handling system, and performs a first memory reference code training. Based on the first memory reference code training, the BIOS discovers a bad DIMM of the DIMMs, and stores information associated with the bad DIMM. The BIOS reboots the information handling system. During the reboot, the BIOS retrieves the information associated with the bad DIMM. The BIOS disables a slot associated with the bad DIMM. In response to the slot being disabled, the BIOS performs a second memory reference code training. Based on the second memory reference code training, the BIOS downgrades the memory system to a closest possible DIMM population.

Abstract: A bus system for a process system, having a first bus subscriber which transmits bus messages and having at least one first bus subscriber which receives bus messages, wherein the transmitting first bus subscriber and the receiving first bus subscriber are connected to one another via a first data bus, wherein the transmitting first bus subscriber is designed such that it transmits control commands to the receiving first bus subscriber, wherein the receiving first bus subscriber is designed such that it executes the control commands of the transmitting first bus subscriber and achieves the object of providing a bus system that is designed to be fail-safe in a special way.

Abstract: A test and measurement system has a test and measurement instrument, a test automation platform, and one or more processors, the one or more processors configured to execute code that causes the one or more processors to receive a waveform created by operation of a device under test, generate one or more tensor arrays, apply machine learning to a first tensor array of the one or more tensor arrays to produce equalizer tap values, apply machine learning to a second tensor array of the one of the one or more tensor arrays to produce predicted tuning parameters for the device under test, use the equalizer tap values to produce a Transmitter and Dispersion Eye Closure Quaternary (TDECQ) value, and provide the TDECQ value and the predicted tuning parameters to the test automation platform.

Abstract: The state transition condition can be adjusted flexibly and easily while taking advantage of the handshake-type technique. A state transition setting screen 11 of an entire state transition flow including a name 12 of each state based on a communication standard and a state transition condition 13 to be executed between states is displayed on a display screen 6a, and input setting for the state transition condition is possible on the state transition setting screen 11.

Abstract: A test and measurement instrument has an input configured to receive a signal from a device under test, a memory, a user interface to allow the user to input settings for the test and measurement instrument, and one or more processors, the one or more processors configured to execute code that causes the one or more processors to: acquire a waveform representing the signal received from the device under test; generate one or more tensor arrays based on the waveform; apply machine learning to the one or more tensor arrays to produce equalizer tap values; and apply equalization to the waveform using the equalizer tap values to produce an equalized waveform; and perform a measurement on the equalized waveform to produce a value related to a performance requirement for the device under test.

Abstract: Disclosed herein is a data processing system comprising a processing unit operable to process data to generate a sequence of outputs, wherein the processing unit is configurable, when generating a sequence of outputs, such that the data processing for generating an output in the sequence of outputs will be performed within a respective processing period for the output. A controller for the processing unit is configured to cause the processing unit, when generating a sequence of outputs, during a respective processing period for at least one output in the sequence of outputs, to also undergo one or more fault detection test(s) such that both processing of data for the output and fault detection testing is performed during the respective processing period for the output.

Abstract: A debug apparatus for performing allocation of target programs in which temperature is uniformized is provided. The debug apparatus receives temperature data measured by temperature sensors from a semiconductor device. The debug apparatus determines, as an analysis result of the temperature data, a CPU where the number of target programs executed is to be decreased and a CPU where the number of target programs executed is to be increased. The debug apparatus changes allocation of the target programs executed by a plurality of CPUs in the semiconductor device based on the analysis result of the temperature data.

Abstract: A stripe reassembling technique includes a stripe server that selects stripes; uses data chunks including valid data in the stripes S1, S2, and S3 as data chunks in a new stripe S4, and generates data of a parity chunk for data of the data chunks in S4 according to an erasure coding (EC) algorithm the same as that of S1, S2, and S3 ; and stores the parity data of the parity chunk on a parity storage node.

Abstract: Software-based solutions may mitigate physical damage to multi-layer networks, such as neural networks having shortcut (residual) connections. An example includes: providing a multi-layer network comprising a plurality of nodes; for each of a plurality of training cases: determining a set of dropout nodes, based at least on a damage model having a probability of a node being selected for dropout that is based at least on a target operating environment of the multi-layer network, wherein the probability of a node being selected is spatially correlated; and training the multi-layer network with the determined set of dropout nodes disabled (with a different set of dropout nodes for different training cases). In some examples the damage model involves expected physical radiation damage to a computing device hosting the multi-layer network, such as on board an aircraft or an earth-orbiting satellite. Thus, multiple degrees of expected damage may be addressed.

Abstract: A method for testing electronic products implemented in an electronic device includes selecting a serial port connected with a slave device in serial communication with a product under test. An activation instruction is transmitted to the slave device, and the electronic product is started through the slave device. Data stored in at least one register of the electronic product and a state of the electronic product is obtained and a capacitance of at least one capacitor in the electronic product is measured. When the electronic product is found to be in an abnormal state, determining a cause of abnormality according to data of the electronic product and the capacitance of the at least one capacitor.