Abstract: A method and device for realizing a snapshot function of a micro-engine processing packet intermediate data, and a computer storage medium. The method comprises: completing a snapshot of packet intermediate data via a debugging instruction to obtain packet snapshot data; completing the storage and outputting of the packet snapshot data according to a software command, so as to move and store the packet snapshot data in an external memory outside the micro-engine; and completing the bus-out of the packet snapshot data in the external memory.

Abstract: A method and system can implement error and event log correlation in an apparatus and include extracting one or more log information associated with a storage location and creating a flexible structure of the one or more log information. The one or more log information is translated to a database store based on a user input. A match level is determined between an event and error data through the one or more log information extracted. When the match level exceeds a predetermined value, a relationship between the event and error data is created through an algorithm and a shareable entry is created for the relationship in a format usable by another apparatus.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor and a non-transitory computer-readable medium having stored thereon a program of instructions executable by the processor. The program of instructions may be configured to, when read and executed by the processor, receive telemetry data associated with one or more information handling resources, receive failure statistics associated with the one or more information handling resources, and correlate the telemetry data and the failure statistics to create training data for a pattern recognition engine configured to predict a failure status of an information handling resource from operational data associated with the information handling resource.

Abstract: An information processing apparatus includes a BIOS storage unit that stores at least a Basic Input Output System (BIOS) program, a main controller that starts up an operating system by executing the BIOS program, and a sub-controller that manages peripheral apparatuses and accesses the BIOS storage unit, in which the sub-controller includes a digest computation unit that computes a digest value on the basis of BIOS program data stored in the BIOS storage unit in parallel to execution of a process in the main controller, and in which the main controller determines validity of the BIOS program on the basis of the digest value.

Abstract: Provided is an image recognition processor. The image recognition processor includes a plurality of nano cores each configured to perform a pattern recognition operation and arranged in rows and columns, an instruction memory configured to provide instructions to the plurality of nano cores in a row unit, a feature memory configured to provide input features to the plurality of nano cores in a row unit, a kernel memory configured to provide a kernel coefficient to the plurality of nano cores in a column unit, and a difference checker configured to receive a result of the pattern recognition operation of each of the plurality of nano cores, detect whether there is an error by referring to the received result, and provide a fault tolerance function that allows an error below a predefined level.

Abstract: A method is disclosed including: obtaining one or more values of a system metric, the system metric being associated with a hardware resource of a computing device; detecting whether the system metric is approaching a threshold, the threshold being associated with a key performance indicator (KPI) of the computing device, the detecting being performed based on the obtained values of the system metric; calculating a predicted value of the system metric in response to detecting that the system metric is approaching the threshold, the predicted value of the system metric being calculated by using a linear predictor that is trained using unevenly-sampled training data; detecting whether the predicted value of the system metric exceeds the threshold; and reconfiguring the computing device to prevent the system metric from reaching the predicted value in response to detecting that the predicted value exceeds the threshold.

Abstract: Embodiments relate to finding correlations between periods of performance degradation of an application and failure rates of the application. Telemetry data reports results of operations performed by the application. The telemetry data is parsed to identify periods of performance degradation of the operations. Performance measures of successful operations during an identified period are aggregated, and performance measures of failed operations during the identified period are aggregated. For the identified periods, conclusions about positive and negative correlation between failures of the operation and degraded performance of the operations are derived based on the aggregate measures of success and failure and based on rates of failure of the operation during the periods.

Abstract: A management device includes: a determiner that, in a plurality of storage area pools each of that has a configuration including a plurality of storage devices, determines a storage area pool into that a spare storage device is incorporated for adding an area storing data; and a manager that incorporates the spare storage device into the determined storage area pool.

Abstract: An information processing apparatus includes a storage unit, a first starter unit that starts up a system program, a second starter unit that starts up an updating program for updating the system program, and a control unit that control to, in a case where the updating program has not been started up normally, start up a recovery program, and output a message prompting a user to attach a storage medium storing a snapshot image of the storage unit including the updating program for updating the system program.

Abstract: A data reception apparatus connected to a data transmission apparatus via transmission paths includes: error detection circuits that are each provided for each of the transmission paths and that each detect an error in received data that has been received from the data transmission apparatus; storage circuits that are each provided for each of the transmission paths and that each store the received data and read the received data at a reported read position at a reported read timing; a selection circuit that selects one of the transmission paths according to error detection results provided by the error detection circuits; and a report circuit that compares received data stored by a storage circuit corresponding to a selected transmission path with received data stored by each of other storage circuits and, according to a comparison result, reports the read timing and the read position to each of the storage circuits.

Abstract: In one example, a system includes an electronic processor configured to receive telemetry data originating from a plurality of client applications. The telemetry data includes data points associated with errors associated with one or more operations. The electronic processor also classifies the telemetry data based a plurality of classes of data, converts the plurality of classes of data into one or more metrics based on a plurality of dimensions, and aggregates the metrics for the classes of data by all the dimensions. The electronic processor accesses a predictive scoring model for a stored metric associated with a dimension of interest, determines a prediction error associated with the dimension of interest, detects an anomaly based on an item selected from the group consisting of the prediction error and a static threshold, and transmits an alert message, generates a bug report, and stores the bug report in a database.

Abstract: A system includes byte-addressable non-volatile memory (NVM) modules. The system includes media controllers communicatively connected to one another over a memory semantic fabric. Each media controller is responsible for a corresponding NVM module to which the media controller is attached. The media controllers cooperatively provide redundant array of independent disks (RAID) functionality at a granularity at which the NVM modules are byte-addressable without employing a master RAID controller.

Abstract: A test case management system includes an input and output (I/O) interface for receiving a first test case, a database (DB) for storing a second test case, and a controller for comparing the first test case with the second test case based on a similarity score between a string of the first test case and a string of the second test case.

Abstract: Technologies are provided for determining an identity of a hardware device that transmitted an error message via a communication bus. A chipset of the communication bus can be configured to transmit an interrupt to an interrupt handler in response to receipt of the error message. The interrupt handler can be configured to determine an identity of the hardware device based on the contents of the error message. The interrupt handler can be configured to transmit a notification to an error remediation service, wherein the notification is associated with the identity of the hardware device. The remediation service can be configured to use the identity of the hardware device to perform one or more error remediation operations. In at least some embodiments, the interrupt handler is configured to store the identifier in a memory and the error remediation service is configured to retrieve the identifier from the memory.

Abstract: An apparatus has two or more processing elements to redundantly process a same processing workload; and divergence detection circuitry to detect divergence between the plurality of processing elements. When a correctable error is detected by error detection circuitry of an erroneous processing element, the erroneous processing element signals detection of the correctable error to another processing element, to control the other processing element to delay processing to maintain a predetermined time offset between the erroneous processing element and the other processing element.

Abstract: A backplane testing system is provided. Based on the connection relationship and signal transfer relationship of a differential signal transceiver, a backplane and a loop device, the differential signal transceiver generates a set of pseudo random binary sequence (PRBS) as a differential signal, and sends the differential signal and receives the returned differential signal, and then determines whether the differential signals sent and received are the same; and the differential signal transceiver generates a test signal that conforms to the IEEE-1149.6 boundary scan test standard, and sends the test signal and receives the returned test signal through a second positive differential signal circuit and a second negative differential signal circuit, and then determines whether the test signals sent and received through the second positive differential signal circuit are the same and whether the test signals sent and received through the second negative differential signal circuit are the same.

Abstract: Computer systems and methods for estimating errors for a quantum system comprising a set of n qubits are provided in which is the projective n-qubit Pauli group for the quantum system, and n is a fixed integer of three or greater. At least a first and second subset of Pauli matrices are identified. The Pauli fidelities f1 of the first subset of Pauli fidelities are estimated. The fixed probability distribution ?2 for the second subset of Pauli matrices are reconstructed using the Pauli fidelities f1 of the first subset of Pauli matrices, thereby estimating errors for the quantum system.

Abstract: A tool includes an interface, a memory, a conversion engine, an identifier tool, and a script engine. The interface communicatively couples the tool to a server. The tool obtains a plurality of visual inputs from a computer program specification document. The memory stores the plurality of visual inputs and a set of known computer code elements. Each respective element of the set of known computer code elements includes predetermined testing criteria for testing computer code that includes the respective element. The conversion engine generates a plurality of textual objects from the plurality of visual inputs. The identifier determines whether each respective textual object matches a respective element of the set of known computer code elements. If a match is found, the identifier tool associates the predetermined testing criteria of the respective element to the respective textual object. The script engine generates a test script using the predetermined testing criteria.

Abstract: Data is received that characterizes a software system. Thereafter, using at least one machine learning model trained using historical testing data from a plurality of training software systems, a recommended computing architecture is generated for the software system. Data can then be provided that characterizes the software system. Related apparatus, systems, techniques and articles are also described.

Abstract: Testing of a software system is initiated in an operating environment. The software system includes a plurality of software programs executing across multiple computing nodes. Thereafter, the operating environment and/or resources available to one or more of the software programs are selectively altered according to a test plan. In addition, functional and/or performance characteristics of one or more parts of the operating environment and/or the software programs under test are also selectively altered according to the test plan. In addition, concurrent with the altering of the operating environment and/or the resources and the altering of functional and/or performance characteristics, behavior and/or performance of the software system are monitored to identify faults.